An interface circuit for an integrated circuit having a plurality of input terminals including chip select, data input, and clock terminals, the interface circuit being operable in accordance with any one of the increment-only, up/down, and SPI interface protocols, the interface circuit comprising:
- interface circuitry coupled to the plurality of input terminals, wherein the interface circuitry processes signals received via the plurality of input terminals in accordance with one of the increment-only, up/down, and SPI interface protocols as determined by a mode selection signal;
- protocol identifying circuitry comprising latch circuits coupled to at least the data input terminal for monitoring signals thereon, and coupled to the interface circuitry for providing the mode selection signal responsive to the detection of a signature within the monitored signals on the data input terminal indicative of a specific one of the increment-only, up/down, and SPI interface protocols;
- and
- reset circuitry for resetting the protocol identifying circuitry to provide a predetermined mode selection signal.