Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
OwnerBin Zhao, Prahalad K. Vasudev +3inventors
InventorsBin Zhao, Prahalad K. Vasudev, Ronald S. Horwath, Thomas E. Seidel, Peter M. Zeitzoff
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Abstract
A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.epsilon. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.
Claims26
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-.epsilon. material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsulated, said integrated circuit comprising:
- an underlying dielectric layer,
- a conductive region comprising deposited copper formed in said underlying dielectric layer, said conductive region having an upper surface,
- a conductive barrier/encapsulation layer selectively formed over said conductive region upper surface,
- a first inter-level dielectric ("ILD") layer formed over said conductive barrier/encapsulation layer and said first dielectric layer, said first ILD layer comprising low-.epsilon. material having a dielectric constant of less than 4,
- a first capping dielectric layer formed over said first ILD layer,
- a second ILD layer formed over said first capping dielectric layer and comprising low-.epsilon. material having a dielectric constant of less than 4,
- a second capping dielectric layer formed over said second ILD layer,
- a via opening extending through said first ILD layer and said first capping layer to the surface of said conductive barrier/encapsulation layer,
- a trench opening extending through said second ILD layer and said second capping layer, and connecting with said via opening,
- a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings, said conductive adhesion/barrier layer connecting to said conductive barrier/encapsulation layer and extending to the top of said second capping dielectric layer;
- continuous copper material filling the volume defined by said conductive adhesion/barrier layer and having a top surface;
- and
- a conductive barrier/encapsulation layer selectively formed over and capping said top surface of said continuous copper material, said conductive barrier/encapsulation layer joining with said conductive adhesion/barrier layer thus to fully encapsulate said continuous copper material.
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-.epsilon. material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsulated, said integrated circuit comprising:
- an underlying dielectric layer having an upper surface,
- a conductive region formed in said underlying dielectric layer, said conductive region having an upper surface,
- a first dielectric separation/barrier layer formed on said upper surfaces of said dielectric layer and said conductive region,
- a first inter-level dielectric ("ILD") layer formed over said first dielectric separation/barrier layer and comprising low-.epsilon. material having a dielectric constant of less than 4,
- a first capping dielectric layer formed over said first ILD layer,
- a second ILD layer formed over said first capping dielectric layer and comprising low-.epsilon. material having a dielectric constant of less than 4,
- a second capping dielectric layer formed over said second ILD layer,
- a via opening extending through said first capping layer, said first ILD layer and said first dielectric separation/barrier layer to said upper surface of said conductive region,
- a trench opening extending through said second ILD layer and said second capping dielectric layer, and connecting with said via opening,
- a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings and extending through said dielectric separation/barrier layer to contact said conductive region;
- continuous conductive material filling the volume defined by said conductive adhesion/barrier layer;
- and
- a second dielectric separation/barrier layer formed over said second capping dielectric layer and said continuous conductive material, said second dielectric separation/barrier layer in conjunction with said conducting barrier layer thus fully encapsulating said continuous conductive material.
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-.epsilon. material are utilized for fabricating the interconnect structure, said integrated circuit comprising:
- an underlying dielectric layer having an upper surface,
- a conductive region formed in said underlying dielectric layer, said conductive region having an upper surface,
- a first dielectric separation/barrier layer formed on said upper surfaces of said underlying dielectric layer and said conductive region,
- a first inter-level dielectric ("ILD") layer formed over said first dielectric separation/barrier layer and comprising low-.epsilon. material,
- a first capping dielectric layer formed over said first ILD layer,
- a second ILD layer formed over said first capping dielectric layer and comprising low-.epsilon. material,
- a second capping dielectric layer formed over said second ILD layer,
- a via opening extending through said first capping layer, said first ILD layer, and said first dielectric separation/barrier layer to said upper surface of said conductive region,
- a trench opening extending through said second ILD layer and said second capping dielectric layer, and connecting with said via opening, and
- a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings and extending through said dielectric separation/barrier layer to contact said conductive region.
Dependencies are inferred from the claim text.