Method of operating a memory having a variable data output length and a programmable register

A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of operation of the memory device comprises:

• receiving an external clock signal;
• receiving first block size information from a bus controller, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request;
• receiving a first request from the bus controller;
• and
• outputting the first amount of data corresponding to the first block size information, in response to the first read request, onto the bus synchronously with respect to the external clock signal.

A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells and a time delay register, the method of operation of the memory device comprises:

• storing a value in the time delay register, the value being representative of a number of external clock cycles to transpire after which the memory device responds to a read request;
• receiving an external clock signal wherein the external clock signal has a fixed frequency;
• receiving block size information from a bus controller, wherein the block size information defines a first amount of data to be output by the memory device onto the bus in response to a read request;
• receiving a first read request from the bus controller;
• outputting the first amount of data corresponding to the block size information onto the bus in response to the first read request,
• wherein the memory device outputs the data synchronously with respect to the external clock signal, during a plurality of clock cycles of the external clock signal and in accordance with the value stored in the time delay register.