Multi-state flash memory defect management

A method of storing data in a flash memory device comprising an array of memory cells arranged in rows and columns, each row of the array having a data portion for storing data, and an overhead portion, the method comprising:

• identifying defective memory cells located in the data portion of a row;
• receiving a stream of data bits to be stored in the array of memory cells;
• selectively removing data bits from the data stream which are intended to be written to the defective memory cells;
• and
• serially storing the removed data bit in the overhead portion of the row.

A method of storing and retrieving data in a memory device, the method comprising:

• receiving an input serial stream of data bits, and storing the input serial stream of data bits in a data location of the memory device wherein at least two of the data bits are stored in one memory cell;
• selectively copying data bits from the input serial stream of data bits and storing the copied data bits in an overhead location of the memory device;
• reading an output serial stream of data bits stored in the data location of the memory device;
• reading the copied data bits from the overhead location of the memory device;
• and
• selectively replacing data bits in the output serial stream of data bits to recreate the received input serial stream of data bits.

A method of storing data in a memory device, the method comprising:

• selecting a current access target location in the memory device;
• comparing a table of known defective memory cell locations in the memory device to the current access target location in the memory device;
• extracting data bits from a plurality of data bits to be stored in the current access target location in the memory device;
• substituting alternate data bits for the extracted data bits;
• storing the plurality of data bits including the alternate data bits in the current access target location;
• and
• storing the extracted data bits in the memory device in a second location.

A data management system comprising:

• a controller to access memory locations in memory devices in response to externally provided commands;
• a defect table register to store a defect table having a plurality of memory addresses of defective memory locations;
• a comparator to compare addresses stored in the defect table to currently accessed memory addresses;
• a plurality of shift registers to store data directed to the defective memory locations;
• and
• substitution circuitry to selectively substitute data in place of the data stored in the shift registers.

A processing system comprising:

• a plurality of n-state flash memory devices each having an array of memory cells arranged in rows and columns, each row of each array including memory cells dedicated to storing overhead data;
• a processor to control read and write operations for the plurality of n-state flash memory devices;
• a defect table register to store a defect table containing addresses of defective memory cells in the plurality of n-state flash memory devices and to store replacement data;
• a compare circuit to compare the addresses of the defect table and an address of a memory location of one of the plurality of n-state flash memory devices to determine if the memory location is defective;
• n-shift registers to serially hold input data intended to be written to defective memory locations;
• substitution circuitry to substitute the replacement data from the defect table in place of the input data intended to be written to defective memory locations prior to writing the input data to one of the n-state flash memory devices;
• and
• memory interface logic to store contents of the n-shift registers in the memory cells dedicated to storing overhead data.

A processing system comprising:

• a flash memory device having an array of memory cells arranged in rows and columns, each row in the array including memory cells to store input data and overhead memory cells to store overhead data;
• a processor to control read and write operations for the flash memory device;
• and
• a remapping circuit coupled between the flash memory device and the processor to transfer data to and from the flash memory device, the remapping circuit comprising:
• a register containing a defect table with addresses of defective memory cells in the flash memory device;
• a compare circuit to compare the addresses in the defect table and an address of a selected memory cell in the flash memory device to determine if the selected memory cell is defective;
• at least one shift register to hold input data intended to be written to the defective memory cells in the flash memory device;
• and
• interface logic to write contents of the shift register to the overhead memory cells.