Virtual logic system for reconfigurable hardware

A reconfigurable hardware apparatus comprising:

• a plurality of reconfigurable devices, each capable of independently implementing a different portion of a circuit, wherein the circuit is characterized by a model partitioned into a plurality of pages, each of the pages corresponding to one of the portions of the circuit;
• and
• a controller coupled to the reconfigurable devices, wherein the controller is operative to control loading of the pages into the devices, such that detection of a condition relating to an unloaded page triggers a subsequent loading of the unloaded page.

An apparatus for reconfiguring a set of hardware to implement different portions of a circuit, the apparatus comprising:

• means for partitioning a model of the circuit into a plurality of pages, each of the pages corresponding to one of the portions of the circuit;
• and
• means for controlling loading of the pages from a memory into the hardware, wherein one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.

An apparatus for reconfiguring a set of hardware to implement different portions of a circuit, the apparatus comprising:

• means for partitioning a model of the circuit into a plurality of pages, each of the pages corresponding to one of the portions of the circuit;
• and
• means for controlling sequential loading of the pages from a memory into the hardware, such that detection of a condition relating to an unloaded page triggers a subsequent loading of the unloaded page.

A reconfigurable hardware apparatus comprising:

• means for implementing different portions of a circuit using reconfigurable hardware, wherein the circuit is characterized by a plurality of pages, each of the pages corresponding to one of the portions of the circuit;
• and
• means for controlling loading of the pages into the reconfigurable hardware, wherein one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.

A reconfigurable hardware apparatus comprising:

• means for implementing different portions of a circuit using reconfigurable hardware, wherein the circuit is characterized by a plurality of pages, each of the pages corresponding to one of the portions of the circuit;
• and
• means for controlling sequential loading of the pages into the reconfigurable hardware, such that detection of a condition relating to an unloaded page triggers a subsequent loading of the unloaded page.

A method of reconfiguring a set of hardware to implement different portions of a circuit, the method comprising the steps of:

• utilizing a plurality of reconfigurable devices to implement different portions of a circuit, wherein the circuit is characterized by a plurality of pages, with each of the pages corresponding to one of the portions of the circuit;
• and
• controlling loading of the pages into the reconfigurable devices, such that one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.

A method of reconfiguring a set of hardware to implement different portions of a circuit, the method comprising the steps of:

• utilizing a plurality of reconfigurable devices to implement different portions of a circuit, wherein the circuit is characterized by a plurality of pages, each of the pages corresponding to one of the portions of the circuit;
• and
• controlling sequential loading of the pages into the reconfigurable devices, such that an inter-page signal directed from a loaded page to an unloaded page is stored at least temporarily until a subsequent loading of the unloaded page.

An apparatus for implementing a circuit in reconfigurable hardware, comprising:

• a circuit partitioner that partitions the circuit into non-pipelinable pages that can be implemented by said reconfigurable hardware;
• and
• a memory for communicating results between a currently implemented one of said non-pipelinable pages and another of said non-pipelinable pages.

An apparatus for implementing a circuit in reconfigurable hardware, said circuit being partitioned into pages and a maximum size page of said pages being implementable on said reconfigurable hardware, said apparatus comprising:

• a page manager for controllably supplying said pages into said reconfigurable hardware in an arbitrary order, wherein said page manager swaps said pages so as to implement said circuit;
• and
• a memory for communicating results between a currently implemented one said pages and another of said pages.

A reconfigurable hardware apparatus comprising:

• a plurality of reconfigurable devices, each capable of independently implementing a different portion of a circuit, wherein the circuit is characterized by a model partitioned into a plurality of pages, each of the pages corresponding to one of the portions of the circuit;
• and
• a controller coupled to the reconfigurable devices, wherein the controller is operative to control loading of the pages into the devices, such that one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.