DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate

A transistor comprising:

• a source region;
• a drain region;
• a channel region between the source and drain regions;
• and
• a floating gate separated from the channel region by a silicon dioxide insulator, wherein the floating gate includes a material selected from the group consisting of gallium nitride (GaN) and gallium aluminum nitride (GaAlN).

A method of using a floating gate transistor having a floating gate electrode that includes a material selected from the group consisting essentially of gallium nitride (GaN) and gallium aluminum nitride (GaAlN), the method comprising:

• storing data by changing the charge of the floating gate;
• reading data by detecting a current between a source and a drain;
• and
• refreshing data based on a data charge retention time that depends upon a barrier energy at an interface between an insulator and the floating gate electrode.

A method of forming a floating gate transistor, the method comprising:

• forming source and drain regions;
• forming a gate insulator from the gate insulator material;
• and
• forming a floating gate from a floating gate material selected from the group consisting essentially of gallium nitride (GaN) and gallium aluminum nitride (GaAlN), such that the floating gate is isolated from conductors and semiconductors.

A memory device comprising:

• a plurality of memory cells, wherein each memory cell includes a transistor comprising:
• a source region;
• a drain region;
• a channel region between the source and drain regions;
• a floating gate separated from the channel region by a silicon dioxide insulator, wherein the floating gate includes a floating gate material selected from the group consisting of gallium nitride (GaN) and gallium aluminum nitride (GaAlN);
• and
• a control gate located adjacent to the floating gate and separated from the floating gate by an intergate dielectric.

A memory device comprising:

• a plurality of memory cells, wherein each memory cell includes a transistor comprising:
• a source region;
• a drain region;
• a channel region between the source and drain regions;
• a floating gate separated from the channel region by a silicon dioxide insulator, wherein the floating gate includes a floating gate material selected from the group consisting of gallium nitride (GaN) and gallium aluminum nitride (GaAlN);
• and
• a control gate located adjacent to the floating gate and separated from the floating gate by an intergate dielectric;
• and
• a refresh circuit to dynamically refresh, at a refresh rate, data stored on the floating gates of the transistors.

A volatile memory device comprising:

• a storage electrode for storing charge, wherein the storage electrode includes a material selected from the group consisting of gallium nitride (GaN) and gallium aluminum nitride (GaAlN);
• a silicon dioxide insulator adjacent to the storage electrode;
• and
• a refresh circuit to dynamically refresh, at a refresh rate, data stored on the storage electrode.

A transistor comprising:

• a source region;
• a drain region;
• a channel region between the source region and the drain region;
• a storage electrode over the channel region, the storage electrode comprising gallium nitride (GaN) or gallium aluminum nitride (GaAlN);
• and
• a silicon dioxide insulator between the storage electrode and the channel region, a barrier energy between the storage electrode and the silicon dioxide insulator being less than approximately 3.3 eV.

A memory device comprising:

• a plurality of memory cells, each memory cell comprising:
• a floating gate comprising gallium nitride (GaN) or gallium aluminum nitride (GaAlN);
• and
• a silicon dioxide insulator adjacent to the floating gate, a barrier energy between the floating gate and the silicon dioxide insulator being less than approximately 3.3 eV.

A transistor comprising:

• a source region;
• a drain region;
• a channel region between the source region and the drain region;
• a storage electrode separated from the channel region by a silicon dioxide insulator, the storage electrode comprising gallium nitride (GaN) or gallium aluminum nitride (GaAlN);
• a control electrode separated from the storage electrode by a dielectric;
• and
• wherein an area of a capacitor formed by the control electrode, the storage electrode, and the dielectric is larger than an area of a capacitor formed by the storage electrode, the silicon dioxide insulator, and the channel region.

A memory cell comprising:

• a source region;
• a drain region;
• a channel region between the source region and the drain region;
• a floating gate separated from the channel region by a silicon dioxide insulator, the floating gate comprising gallium nitride (GaN) or gallium aluminum nitride (GaAlN);
• a control gate separated from the floating gate by a dielectric;
• and
• wherein an area of a capacitor formed by the control gate, the floating gate, and the dielectric is larger than an area of a capacitor formed by the floating gate, the silicon dioxide insulator, and the channel region.

A memory device comprising:

• a plurality of memory cells, each memory cell comprising:
• a source region;
• a drain region;
• a channel region between the source region and the drain region;
• a floating gate separated from the channel region by a silicon dioxide insulator, the floating gate comprising gallium nitride (GaN) or gallium aluminum nitride (GaAlN);
• a control gate separated from the floating gate by a dielectric;
• and
• wherein an area of a capacitor formed by the control gate, the floating gate, and the dielectric is larger than an area of a capacitor formed by the floating gate, the silicon dioxide insulator, and the channel region.