Data processing system using a shared register bank and a plurality of processors
AssigneesSharp Electronics Corporation, Sharp Kabushiki Kaisha
InventorSteven B. Sidman
Life of this patent
Estimating the term…
Abstract
A system and method is provided for use in register-based CPUs for simultaneously processing data in a series of CPU register banks while concurrently loading and unloading data into additional register banks. The register banks then sequentially shared between arithmetic processors connected to the CPU datapath. Each register bank, after being loaded with data, is connected to a plurality of data processors in sequence and the data in each register bank is processed. The data is not moved between register banks within the datapath, except when it is loaded and unloaded from the datapath. The invention takes advantage of the shorter time required to move control signals, as compared with moving data.
Claims10
A register-based CPU datapath for use in processing data from selected external data sources and for supplying processed data to selected destinations, the register-based CPU datapath comprising:
- a plurality of data storage register banks each having one or more input/output ports through which operative connections to said register banks are effected;
- a plurality of arithmetic processors for processing data in one or more of said data storage register banks when operatively connected to an arithmetic processor;
- a CPU datapath interconnect system for operatively connecting said register banks to selected arithmetic processors in the CPU datapath and to selected data sources and destinations outside of the CPU datapath;
- and
- an interconnect controller for providing control signals which operatively connect each register bank to a sequence of selected devices, said sequence including:
- a) operatively connecting a register bank to a data source to load data into the register bank;
- b) operatively connecting the register bank to a first of said arithmetic processors to process data in accordance with said first arithmetic processor;
- c) operatively connecting the register bank to a second of said arithmetic processors to process data in accordance with said second arithmetic processor;
- and
- d) operatively connecting the register bank to a data destination for unloading of the data from the register bank to the data destination;
- said interconnect controller operatively connecting one or more additional register banks to said selected devices in said sequence, whereby the data in each register bank is processed through a sequence of arithmetic processors.
A data processing method for use in a register-based CPU datapath, the CPU datapath including a plurality of data storage register banks each having one or more input/output ports through which operative connections to the register banks are effected, a plurality of arithmetic processors for processing data, and a CPU datapath interconnect system for providing operative connections between the register banks and the arithmetic processors, the method comprising;
- loading data into a first register bank in the CPU datapath;
- operatively connecting the first register bank to a first arithmetic processor to process data therein in accordance with the first arithmetic processor;
- operatively connecting the first register bank to a second arithmetic processor to process data in accordance with the second arithmetic processor;
- unloading the data from said first register bank to a data destination, whereby the data in said first register bank is processed through a sequence of arithmetic processors.
Dependencies are inferred from the claim text.