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US 6,029,187 AGranted
Fast regular multiplier architecture
AssigneeAtmel Corporation
InventorIngrid Verbauwhede
Life of this patent
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Abstract
A multiplier architecture in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure in order to achieve a small floor plan when reduced to silicon. A Hekstra-type multiplier is modified by replacing full adders circuits with compressor circuits in a manner that preserves the balance of the signal propagation delays. The result is an architecture having a regular layout that greatly facilitates its implementation in silicon.
Claims17
A multiplication circuit, comprising:
- means, receiving an M-bit multiplicand and an N-bit multiplier, for forming N M-bit partial products, where M and N are integers greater than 8, each bit of each partial product having a bit-significance corresponding to a specified bit of an (M+N)-bit product;
- and
- addition means for summing said N M-bit partial products such that bits of said partial products having the same bit-significance are added together, wherein said addition means is organized into an architecture that is characterized by a plurality of subarrays forming partial sums and a multistage main array adding said partial sums, said architecture having an asymmetric but non-inherently delay-balanced branching architecture in which a first main array stage receives partial sums from two subarrays and each subsequent main array stage receives partial sums from one previous main array stage and only one corresponding subarray, the subarray for each subsequent main array stage being successively larger than subarrays for previous main array stages to maintain balanced propagation delays for partial sums provided to each main array stage, at least one subarray including a four-to-two compressor circuit therein, each signal propagation path from a first stage of a subarray through subsequent stages of said subarray to a stage of said main array and through subsequent stages of said main array having an identical number of compressor circuits compared to all other signal propagation paths, and
- each compressor circuit having four signal inputs connected to outputs from a previous stage and an extra carry input connected to a carry output from a same stage of next lower bit significance, and also having sum and carry signal outputs connected to signal inputs of a subsequent stage and an extra carry output connected to a carry input for a same stage of next higher bit significance, wherein a state of said extra carry output is derived from states of all four of said signal inputs but not from said extra carry input and states of said sum and carry signal outputs are derived from all four of said signal inputs and said extra carry input, said extra carry input operating on a result of operation upon all four signal inputs to derive said sum and carry signal output states, said sum signal output having a state set to 1 if the number of 1's in said four signal inputs and said extra carry input is odd, said sum signal output being set to 0 otherwise, said carry signal output and said extra carry output being both set to 1 if the number of 1's in said four signal inputs and extra carry input is 4 or 5, one and only one of said carry signal output and said extra carry output being set to 1 if the number of 1's in said four signal inputs and extra carry input is 2 or 3, and said carry signal output and said extra carry output being both set to 0 if the number of 1's in said four signal inputs and extra carry input is 0 or 1;
- a vector merging adder receiving a multibit sum word and a multibit carry word together representing a partial sum from a final main array stage of said addition means, said vector merging adder summing said sum word and carry word to produce said (M+N)-bit product.
2 more elements
A multiplication circuit, comprising:
- means, receiving an M-bit multiplicand and an N-bit multiplier, for forming partial product terms therefrom, each partial product term corresponding to a specified bit of an (M+N)-bit product;
- and,
- for each product bit, addition means for adding all partial product terms that correspond to that product bit plus any carry terms generated by the addition means for the next less significant product bit, each said addition means generating a sum forming said product bit and one or more carry terms to be transferred to the addition means for the next greater significant product bit,
- wherein each said addition means is organized into an asymmetric, non-inherently delay balanced architecture that is characterized by a plurality of adding stages forming partial sums, the adding stages being organized into a plurality of chains of successive subarray adders and a single chain of successive main array adders, a first stage in said chain of main array adders being an adder connected to two chains of subarray adders to receive partial sums therefrom, each stage of said chain of main array adders subsequent to said first stage being connected to a preceding stage of said main array adder chain and to one and only one chain of subarray adders,
- wherein each adding stage in said chain of main array adders being a four-to-two compression adder circuit, hereafter called a `compressor`, said two chains of subarray adders connected to said first stage of said main array being identical in the number of each type of adder in those chains, each chain of subarray adders connected to subsequent stages of said main array being identical to a chain of subarray adders connected to a preceding stage of said main array in the number of each type of adder in that chain except for having one more compressor than said preceding chain, whereby each signal propagation path through said chains of subarray adders and through said main array has a balanced delay,
- each compressor circuit having four signal inputs connected to outputs from a previous stage and an extra carry input connected to a carry output from a same stage of next lower bit significance, and also having sum and carry signal outputs connected to signal inputs of a subsequent stage and an extra carry output connected to a carry input for a same stage of next higher bit significance, wherein a state of said extra carry output is derived from states of all four of said signal inputs but not from said extra carry input and states of said sum and carry signal outputs are derived from all four of said signal inputs and said extra carry input, said extra carry input operating on a result of operation upon all four signal inputs to derive said sum and carry signal output states, said sum signal output having a state set to 1 if the number of 1's in said four signal inputs and said extra carry input is odd, said sum signal output being set to 0 otherwise, said carry signal output and said extra carry output being both set to 1 if the number of 1's in said four signal inputs and extra carry input is 4 or 5, one and only one of said carry signal output and said extra carry output being set to 1 if the number of 1's in said four signal inputs and extra carry input is 2 or 3, and said carry signal output and said extra carry output being both set to 0 if the number of 1's in said four signal inputs and extra carry input is 0 or 1;
- wherein compressors in stages of said chain of subarray adders other than a first stage are asymmetric compressors in which two inputs to said compressors propagate slower than two other inputs to sum and carry outputs of said compressors, and
- subsequent to said addition means, a vector merging adder receiving a multibit sum word and a multibit carry word from the addition means for each product bit, said vector merging adder summing corresponding bits of the same bit significance of said sum word and said carry word to form said (M+N)-bit product.
5 more elements
A multiplication circuit, comprising:
- means, receiving an M-bit multiplicand and an N-bit multiplier, for forming partial product terms therefrom, each partial product term corresponding to a specified bit of an (M+N)-bit product;
- and,
- for each product bit, addition means for adding all partial product terms that correspond to that product bit plus any carry terms generated by the addition means for the next less significant product bit, each said addition means generating a sum forming said product bit and one or more carry terms to be transferred to the addition means for the next greater significant product bit,
- wherein each said addition means is organized into an asymmetric, non-inherently delay-balanced architecture that is characterized by a plurality of adding stages forming partial sums, the adding stages being organized into a plurality of chains of successive subarray adders and a single chain of successive main array adders, a first stage in said chain of main array adders being an adder connected to two chains of subarray adders to receive partial sums therefrom, each stage of said chain of main array adders subsequent to said first stage being connected to a preceding stage of said main array adder chain and to one and only one chain of subarray adders,
- wherein each adding stage in said chain of main array adders being a four-to-two compression adder circuit, hereafter called a `compressor`, each compressor having a delay being less than a delay associated with a pair of successive full adders, said two chains of subarray adders connected to said first stage of said main array being identical in the number of each type of adder in those chains, each chain of subarray adders connected to subsequent stages of said main array being identical to a chain of subarray adders connected to a preceding stage of said main array in the number of each type of adder in that chain except for having one more compressor than said preceding chain, whereby each signal propagation path through said chains of subarray adders and through said main array has a balanced delay,
- each compressor circuit having four signal inputs connected to outputs from a previous stage and an extra carry input connected to a carry output from a same stage of next lower bit significance, and also having sum and carry signal outputs connected to signal inputs of a subsequent stage and an extra carry output connected to a carry input for a same stage of next higher bit significance, wherein a state of said extra carry output is derived from states of all four of said signal inputs but not from said extra carry input and states of said sum and carry signal outputs are derived from all four of said signal inputs and said extra carry input, said extra carry input operating on a result of operation upon all four signal inputs to derive said sum and carry signal output states, said sum signal output having a state set to 1 if the number of 1's in said four signal inputs and said extra carry input is odd, said sum signal output being set to 0 otherwise, said carry signal output and said extra carry output being both set to 1 if the number of 1's in said four signal inputs and extra carry input is 4 or 5, one and only one of said carry signal output and said extra carry output being set to 1 if the number of 1's in said four signal inputs and extra carry input is 2 or 3, and said carry signal output and said extra carry output being both set to 0 if the number of 1's in said four signal inputs and extra carry input is 0 or 1;
- wherein compressors in stages of said chain of subarray adders other than a first stage are asymmetric compressors in which two inputs to said compressors propagate slower than two other inputs to sum and carry outputs of said compressors, and
- subsequent to said addition means, a vector merging adder receiving a multibit sum word and a multibit carry word from the addition means for each product bit, said vector merging adder summing corresponding bits of the same bit significance of said sum word and said carry word to form said (M+N)-bit product.
5 more elements
Dependencies are inferred from the claim text.