Pipeline analog-to-digital conversion that reduces the accumulation offset errors

A pipeline A/D-converter for converting an analog input signal V.sub.in into a digital output signal of a predetermined number, n, of output bits b.sub.i by using a predetermined reference signal V.sub.r, where i is an integer ranging from 1 to n, said pipeline A/D-converter comprising:

• means for generating the output bits b.sub.i according to a Gray coding algorithm defined by the following equations:
• V.sub.in (i=1)=V.sub.in
• V.sub.o (i)={2.multidot.V.sub.in (i)+(-1).sup.b.sbsp.i .multidot.V.sub.r }.multidot.(-1).sup.b.sbsp.i (1.ltoreq.i.ltoreq.n-1);
• V.sub.in (i+1)=V.sub.o (i)
• and ##EQU24##

A pipeline stage for a pipeline A/D-converter, wherein the pipeline stage is responsive to an analog input signal and a predetermined reference signal, the pipeline stage comprising:

• a comparator for generating an output bit in response to the analog input signal;
• a sample-and-hold circuit for sampling and holding the analog input signal;
• an amplifying circuit for amplifying the sampled and held signal by a factor of 2;
• means for selectively, in dependence on the generated output bit, adding and subtracting the predetermined reference signal to the output signal of the amplifying circuit;
• and
• means for selectively, in dependence on the generated output bit, inverting the output signal of the amplifying circuit,
• wherein the comparator, the sample-and-hold-circuit, the amplifying circuit, the means for selectively adding and subtracting, and the means for selectively inverting are controlled by clock signals generated by a clock signal generator.

A pipeline stage for a pipeline analog-to-digital (AID) converter, wherein the pipeline stage is responsive to a differential analog input signal and a predetermined differential reference signal, the pipeline stage comprising:

• a comparator for generating an output bit in response to the differential input signal;
• switch-capacitor units responsive to the differential input signal and the predetermined differential reference signal, and having first capacitors and second capacitors, first control switches for selectively connecting the differential input signal to the first and second capacitors, and second control switches for selectively, depending on the generated output bit, shifting the polarity of the differential reference signal and for selectively connecting the selectively polarity shifted differential reference signal to the first capacitors, the first and second capacitors being charged in response to the differential input signal and the selectively polarity shifted differential reference signal;
• an operational amplifier having two input terminals and two output terminals, each one of the input terminals being connected to a respective one of the switch-capacitor units with each one of the second capacitors of the switch-capacitor units selectively connected in parallel over a respective pair of input-output terminals of the operational amplifier;
• and
• a switch arrangement connected to the output terminals of the operational amplifier for selectively, depending on the output bit, interchanging the polarity of the output signal of the operational amplifier,
• wherein the comparator, the first and second control switches, and the switch arrangement are controlled by clock signals generated by a clock signal generator.

A method for pipeline A/D-conversion of an analog input signal V.sub.in into a digital output signal of a predetermined number, n, of output bits b.sub.i by using a predetermined reference signal V.sub.r, where i is an integer ranging from 1 to n, said method comprising the step of:

• generating the output bits according to a Gray coding algorithm defined by the following equations:
• V.sub.in (i=1)=V.sub.in
• V.sub.o (i)={2.multidot.V.sub.in (i)+(-1).sup.b.sbsp.i .multidot.V.sub.r }.multidot.(-1).sup.b.sbsp.i (1.ltoreq.i.ltoreq.n-1);
• V.sub.in (i+1)=V.sub.o (i)
• and ##EQU25## 10.

A pipeline stage for a pipeline A/D-converter, said pipeline stage having an analog input terminal, an analog output terminal and a digital output terminal, the analog input terminal being responsive to an analog signal, said pipeline stage comprising:

• a comparator for generating an output bit in response to said analog signal, and for applying said output bit to said digital output terminal;
• means for subjecting said analog signal to a sample and hold operation, to an amplification by two, selectively, depending on said generated output bit, to a signal inversion, and to an addition of a predetermined reference signal such as to generate an analog output signal of said stage;
• and
• means for applying said analog output signal to said analog output terminal.