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AssigneeHitachi, Ltd.
InventorsMasahiko Ogino, Akira Nagai, Shuji Eguchi, Toshiaki Ishii, Masanori Segawa, Haruo Akahoshi, Akio Takahashi, Takao Miwa, Naotaka Tanaka, Ichirou Anjou
Estimating the term…
A semiconductor device has a multi-layered wiring structure having a conductor layer to be electrically connected to a packaging substrate, the structure being provided on a circuit formation surface of a semiconductor chip; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate, after packaging thereof, and multiple wiring layers. In this semiconductor device, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase the signal speed; the distance between a ground layer and a power supply layer is shortened, to reduce noise produced upon operation, and also a thermal stress upon packaging is relieved by the buffer layer of the multi-layered wiring structure, resulting in the improved connection reliability; and the number of terminals per unit is increased because of elimination of wire bonding.
A semiconductor device comprising:
A semiconductor device comprising:
A packaging structure comprising:
A packaging structure comprising:
Dependencies are inferred from the claim text.