Instruction folding for a stack-based machine

A method for decoding virtual machine instructions in a virtual machine instruction processor the method comprising:

• (a) determining if a first virtual machine instruction of a virtual machine instruction sequence is an instruction for pushing a first operand value onto the operand stack fom a data store merely as a first source operand for a second virtual machine instruction;
• if the result of the (a) determining is affirmative, supplying an execution unit with a single folded operation equivalent to a foldable sequence comprising the first and second virtual machine instructions, the single folded operation including a first operand identifier selective for the first operand value, thereby obviating an explicit operation corresponding to the first virtual machine instruction;
• and
• if the result of the (a) determining is negative, supplying the execution unit with an operation equivalent to the first virtual machine instruction in the virtual machine instruction sequence.

A stack-based virtual machine implementation comprising:

• a randomly-accessible operand stack representation;
• a randomly-accessible local variable storage representation;
• a virtual machine instruction decoder for selectively decoding virtual machine instrnctions and folding together a selected sequence thereof to eliminate unnecessary temporary storage of operands on the operand stack;
• and
• a hardware virtual machine instruction processor including a hardware stack cache, a hardware virtual machine instruction decoder, and an execution unit;
• wherein the randomly-accessible operand stack local variable storage representations at least partially reside in the hardware stack cache, wherein the virtual machine instruction decoder comprises the hardware instruction decoder coupled to provide the execution unit with Op-code, operand, and result identifiers respectively selective for a hardware virtual machine instruction processor operation and for locations in the hardware stack cache as a single hardware virtual machine instruction processor operation equivalent to the selected sequence of virtual machine instructions.

A hardware virtual machine instruction processor comprising:

• an instruction cache unit including:
• an instruction cache;
• and
• an instruction buffer;
• an integer execution unit including:
• an instruction decode unit comprising:
• a normal decode path;
• a fold decode path for decoding a sequence of virtual machine instructions from the instruction buffer and, if the sequence is foldable, supplying a single operation identifier, operand identifiers, and a destination identifier together equivalent to the sequence of virtual machine instructions;
• and
• a switch complex responsive to the folded decode path for selecting operation, operand, and destination identifiers from the folded decode path in response to a foldable sequence indication therefrom, and otherwise selecting operation, operand, and destination identifiers from the normal decode path;
• an integer unit coupled to the switch complex for executing in accordance with operation, operand and destination identifiers selected thereby;
• and
• a stack management unit coupled to the integer execution unit for representing operand stack and data store locations identified by the selected operand and destination identifiers.