US 6,026,464 A · Memory control system and method utilizing distributed memory controllers for multibank memory

Abstract

A memory control system and method for controlling access to a global memory. The global memory has multiple memory banks coupled to a memory bus. Multiple memory controllers are coupled between processing devices and the memory bus. The memory controllers control access of the processing devices to the multiple memory banks by independently monitoring the memory bus with each memory controller. The memory controllers track which processing devices are currently accessing which memory banks. The memory controllers overlap bus transactions for idle memory banks. The bus transactions include a control bus cycle that initially activates the target memory bank and data bus cycles that transfer data for previously activated memory banks. A control bus arbiter coupled to the memory bus grants activation of the multiple memory banks according to a first control bus request signal and a separate data bus arbiter operating independently of the control bus arbiter grants data transfer requests according to a second data bus request signal.

Claims19

Dependent claims

A memory system, comprising:

a main memory having multiple memory banks;
a memory bus coupled to the main memory;
multiple memory controllers each coupled between an associated processing device and the memory bus, the memory controllers each controlling access of the associated processing device to the multiple memory banks by independently monitoring which memory controllers are accessing each of the multiple memory banks, the memory controllers each generating a first control bus arbitration request signal for arbitrating activation for one of the memory banks over the memory bus and separately generating a second data bus request signal after the first control bus request signal, the second data bus request signal for arbitrating data transfers between the associated processing device and one of the memory banks activated pursuant to the first control bus arbitration request signal.

A method for controlling access by processing devices through a memory bus to a global memory having multiple memory banks, comprising:

providing memory controllers between each processing device and the memory bus;
independently monitoring with each of the memory controllers, requests by any one of the processing devices to access any one of the memory banks;
independently tracking and maintaining with each of the memory controllers memory bank states identifying the processing devices accessing each of the memory banks;
controlling with the memory controllers when the processing devices request the global memory by generating a first control bus arbitration request signal that requests activation for a first one of the memory banks over the memory bus according to the tracked memory bank states;
and
separately generating a first data bus arbitration request signal after the first control bus arbitration request signal that initiates transfer of data between one of the processing devices and the first one of the memory banks after the requested first one of the memory banks is activated pursuant to the first control bus arbitration request signal.

3 more elements

Dependencies are inferred from the claim text.

Memory control system and method utilizing distributed memory controllers for multibank memory

Life of this patent

Memory control system and method utilizing distributed memory controllers for multibank memory

Life of this patent

Abstract

Claims19