US 6,026,230 A · Memory simulation system and method

Abstract

The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. The Memory Mapping aspect of the invention provides a structure and scheme where the numerous memory blocks associated with the user's design is mapped into the SRAM memory devices in the Simulation system instead of inside the logic devices, which are used to configure and model the user's design. The Memory Mapping or Memory Simulation system includes a memory state machine, an evaluation state machine, and their associated logic to control and interface with: (1) the main computing system and its associated memory system, (2) the SRAM memory devices coupled to the FPGA buses in the Simulation system, and (3) the FPGA logic devices which contain the configured and programmed user design that is being debugged.

Claims20

Dependent claims

A memory mapping system for mapping at least one memory block from at least one logic device to at least one memory device in a reconfigurable hardware unit, the reconfigurable hardware unit including a bus controller, at least one logic device for modeling at least a portion of the user design in hardware where the hardware model has at least one memory block and associated user memory interface, at least one memory device, a bus subsystem coupling at least one logic device, at least one memory device, and the bus controller, the memory mapping system comprising:

a bus driver coupled to the bus subsystem;
a memory block interface coupled to the bus driver, the bus subsystem, and the user memory interface to handle write/read memory access between at least one logic device and at least one memory device, at least one memory device storing the memory blocks associated with the hardware model;
and
an evaluation logic in each logic device coupled to the hardware model, the bus driver, the memory block interface, and the bus controller for providing evaluation control signals, the evaluation control signals used to evaluate data in the hardware model and to control write/read memory access between at least one logic device and at least one memory device via the bus driver and the memory block interface.

1 more element

A simulation system operating in a host computer system for simulating a behavior of a circuit, the host computer system including a central processing unit (CPU), main memory, a local bus coupling the CPU to main memory and allowing communication between the CPU and main memory, and a system bus, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:

a software model of the circuit coupled to the local bus;
software control logic coupled to the software model and a hardware logic element, for controlling the operation of the software model and said hardware logic element, including
interface logic which is capable of receiving input data and a clock signal from an external process, and
clock detection logic for detecting an active edge of the clock signal and generating a trigger signal;
and
said hardware logic element coupled to the system bus and including
a system bus controller,
a hardware model bus coupled to the system bus controller,
at least one logic device and at least one memory device coupled to the hardware model bus,
a hardware model of at least a portion of the circuit residing in at least one logic device, the hardware logic element including clock enable logic for evaluating data in the hardware model in response to the trigger signal, and
a memory mapping system for mapping at least one memory block associated with the circuit in the hardware model from at least one logic device to at least one memory device.

8 more elements

Dependencies are inferred from the claim text.

Memory simulation system and method

Life of this patent

Memory simulation system and method

Life of this patent

Abstract

Claims20