Driving device, a column electrode driving semiconductor integrated circuit and a row electrode driving semiconductor integrated circuit used for a liquid crystal display device

A semiconductor integrated circuit for driving column electrodes in a liquid crystal display device to be driven by a multiple line selection method, said semiconductor integrated circuit being used for a liquid crystal display device having a select and output circuit unit which selects a specified voltage value among voltage values having a number of levels corresponding to a number of simultaneously selected row electrodes, and which applies the selected voltage value to each column electrode, the semiconductor integrated circuit comprising:

• a memory unit including a control circuit for storing display data and outputting data on each row electrode in simultaneously selected lines, wherein the memory unit comprises at least one of metal oxide semiconductor field effect transistors and complementary metal oxide semiconductors and has a memory column capacity in a memory column direction wherein a number of memories for columns is equal to a number of outputs for columns when memory cells of 1 bit per 1 pixel are used, or a memory column capacity of two times when a gray shade display is effected;
• memory signals of at least one of a data signal, a write or read signal, and an address signal as signals to be accessed to the memory cells;
• and
• an arithmetic circuit unit including an arithmetic processing circuit provided for an output of each column electrode, said arithmetic processing circuit producing, by arithmetic processing, information of voltages selected by the select and output circuit unit by receiving data output from the memory unit and selection data indicating a voltage pattern applied to the selected row electrodes;
• wherein a memory cell of 1 bit has a first node electrode for a first MOS FET which is connected to a data line D and has a second node electrode for an input to a first CMOS inverter and an output to a second CMOS inverter, a second MOS FET has a first node electrode connected to a data line D and a second node electrode connected to an output side of the first CMOS inverter and functioning as an input terminal for the second CMOS inverter, and a gate electrode for switch-controlling of the first and second MOS FETs are connected to a word line.