Fast reprogrammable logic with active links between cells

A field programmable gate array, comprising:

• a plurality of logic blocks that needs to be connected together in a programmable way to implement a desired function for said field programmable gate array;
• a plurality of input/output pins;
• a connection matrix coupling said logic blocks together or to said input/output pins in a programmable manner to form a circuit capable of carrying out a desired function specified by a user of said field programmable gate array, said connection matrix characterized by a plurality of conductors coupled to signal inputs and signal outputs of said logic blocks or to said input/output pins and programmably coupled to each other at every one of a plurality of programmable connection sites by programmable active links, each active link being programmable to present either a high impedance path or a low impedance path between two or more circuit nodes or conductors coupled to said active link, and each active link comprised of one or more MOS transistors coupled as an inverter or buffer amplifier driving a totem pole, push-pull tristate output stage having MOS pull-up and pull-down transistors and enabling circuitry including a memory cell for holding a programming bit that defines whether said active link is enabled or disabled by said enabling circuitry, said input and output of said active link being coupled, respectively, to the gates of said pull-up and pull-down transistors through said enabling circuitry, each said active link being coupled to high and low rail conductors of an external power supply, said active link functioning to perform a repeater function on the input signal propagating through said active link to reconstruct said signal by reducing the rise and fall times of pulses in said input signal by turning on or off the MOS pull-up or pull-down transistors of said output stage in response to the logic state said input signal thereby causing said external power supply to charge or discharge any parasitic capacitance load coupled to an output of said active link to simultaneously reproduce said logic transitions of said input signal while reducing the rise times and fall times of said logic transitions as it propagates through said active link when enabled but to present a high impedance to said output when said active link is disabled so as to prevent current from leaking from said output to said input or vice versa and isolating said output from said external power supply.

A process for manufacturing a field programmable gate array connection matrix on the integrated circuit die containing a field programmable gate array, comprising:

• forming a connection matrix on said field programmable gate array comprised of a plurality of conductors which are insulated from each other;
• and
• forming a plurality of programmable active links with one or more programmable active links at every location of a programmable connection in said connection matrix so as to selectively couple the signal propagating in a conductor of said connection matrix coupled to an input of said active link to another conductor of said connection matrix coupled to an output of said active link, each active link comprised of an MOS inverter coupled to high and low rail conductors of an external power supply and driving a tristate output stage also coupled to high and low rail conductors of an external power supply and enabling circuitry including a memory call for holding a programming bit that defines whether said active link is enabled or disabled by said enabling circuitry, and having enabling circuitry having an input for receiving an enabling signal having an enable state which causes said active link to operate as a repeater and a disable state which causes said output stage to enter tristate mode so as to isolate said output of said active link from said input and from said external power supply, said active link structured such that, when enabled and acting as a repeater said active link causes said output stage to selectively couple the high or low rail conductors of said external power supply to said output of said active link so as to charge or discharge the parasitic capacitances coupled to said output in response to the logic transitions of said signal propagating in said conductor coupled to said input of said active link thereby causing decreases in the rise times and fall times of logic transitions on said output corresponding to logic transitions on said input.

A process for selectively coupling signals from one circuit to another on a field programmable gate array through a connection matrix having a plurality of conductors and a plurality of programmable active links at every programmable connection point in said connection matrix so as to implement a desired functionality for said field programmable gate array, each active link being comprised of one or more transistors connected so as to use transistor action to selectively couple the high and low rail conductors of an external power supply to the output load on said active link and having enabling circuitry including a memory cell to store a programming bit the state of which causes said enabling circuitry to enable or disable said active link, comprising:

• generating programming signals suitable to selectively enable the appropriate ones of said active links so as to connect a plurality of said conductors together to form a plurality of data paths through said connection matrix suitable to cause said field programmable gate array to have the desired functionality;
• and
• as a signal propagates through each said active link of each said data path, using the transistor action of each active link to selectively couple either said high or low rails of said external power supply to the output of said active link in accordance with the logic transitions of the input signal to said active link thereby reproducing said logic transitions while simultaneously speeding up the rise or fall times thereof.

A field programmable gate array, comprising:

• a plurality of logic circuits having inputs and outputs;
• a connection matrix comprised of horizontal buses, vertical buses, input/output pins and a plurality of programmable connection points that are programmed to be either enabled or disabled so as to define a plurality of data paths through said connection matrix, each comprising an active link, said active links making programmable connections between said inputs and outputs of said logic blocks and individual conductors of said horizontal and vertical buses and between individual conductors of said horizontal and vertical buses and between said individual conductors of said horizontal and vertical buses and said input/output pins;
• each said active link comprising an inverting or non inverting transistor amplifier with a tristate output stage coupled to high and low rails of an external power supply and enabling circuitry including a memory cell for holding a programming bit that declines whether said active link is enabled or disabled, each said active link comprised of one or more transistors coupled as a buffer amplifier or inverter coupled to high and low rails of an external power supply so as to use transistor action to selectively couple said high or low rail conductors of said external power supply to said output of said active link in accordance with logic transitions at the input of said active link so as to reproduce said logic transitions on said output while simultaneously decreasing the rise and fall times thereof.

A programmable coupling structure in a field programmable gate array, comprising:

• a first segment of a high speed data line in said field programmable gate array;
• a second segment of a high speed data line in said field programmable gate array;
• one or more active links, each comprised of one or more MOS transistors connected as an inverting or noninverting buffer amplifier with a tristate output stage and enabling circuitry having an enable input for receiving an enable signal and coupled to a memory cell for storing a programming bit which defines the logic state of said enable signal, each having an input coupled to said first segment and an output coupled to said second segment, said active link functioning to couple data signals on said first segment to said second segment while reducing the rise and fall times of logic transitions in said data signals;
• and wherein said enabling circuitry comprises one or more MOS steering transistors coupled to said amplifier and tristate output stage in such a way as to render said amplifier and/or output stage inoperative such that no coupling of data signals on said first segment is made to said second segment and such that said second segment is isolated from said first segment and from said high and low rails of said external power supply when said programming bit is in a first logic state and so as to enable said amplifier and output stage so as to couple data signals on said first segment to said second segment and use transistor action to selectively couple said high or low rail conductors of said external power supply to said second conductor to drive any parasitic capacitance or other load coupled therto in accordance with said digital signal on said first conductor so as to decrease the rise and fall times of the digital signals propagating on said second conductor when said programming bit is in a second logic state.

A field programmable gate array, comprising:

• a plurality of logic blocks that needs to be connected together in a programmable way to implement a desired function for said field programmable gate array;
• a plurality of input/output pins;
• a connection matrix coupling said logic blocks together or to said input/output pins in a programmable manner to form a circuit capable of carrying out a desired function specified by a user of said field programmable gate array, said connection matrix characterized by a plurality of conductors coupled to signal inputs and signal outputs of said logic blocks or to said input/output pins and programmably coupled to each other at substantially every one of a plurality of programmable connection sites by programmable active links, each active link being programmable by storing a bit in a memory cell coupled to enabling circuitry in said active link to present either a high impedance path or a low impedance path between an input and an output of said active link, and each active link coupled to the high and low rail conductors of an external power supply and structured to selectively couple said high and low rail conductors to said output in accordance with the state of a digital signal on said input such that the signal propagating through said active link has its rise times or fall times reduced;
• and wherein each said active link is comprises:
• a differentially coupled buffer amplifier having an output;
• a first emitter follower means coupled between said high and low rail conductors and coupled to said output of said buffer amplifier.

A field programmable gate array, comprising:

• a plurality of logic blocks that needs to be connected together in a programmable way to implement a desired function for said field programmable gate array;
• a plurality of input/output pins;
• a connection matrix coupling said logic blocks together or to said input/output pins in a programmable manner to form a circuit capable of carrying out a desired function specified by a user of said field programmable gate array, said connection matrix characterized by a plurality of conductors coupled to signal inputs and signal outputs of said logic blocks or to said input/output pins and programmably coupled to each other at substantially every one of a plurality of programmable connection sites by programmable active links, each active link being programmed to present either a high impedance path or a low impedance path between two or more circuit nodes or conductors coupled to said active link, and each active link structured to amplify the signal propagating through said active link with a gain sufficiently high to substantially reduce the amount of degradation of rise times or fall times in signals propagating through said active links compared to the amount of degradation of rise times or fall times in the same high speed signals propagating through a like number of passive links in the form of pass transistors in prior art field programmable gate arrays;
• and wherein each said active link is comprises:
• a high rail conductor and a low rail conductor for coupling to a voltage source for developing a potential difference therebetween;
• first and second data inputs, and first and second data outputs;
• a first emitter follower means coupled between said high and low rail conductors for programmably coupling data signals from said first data input to either, neither or both of said first and second data outputs while applying a gain of approximately one or more to data signals propagating therethrough while providing a desired amount of voltage level shifting of the signal levels propagating therethrough and a desired amount of additional current drive capacity over the current drive capacity of whatever circuit is driving said first data input;
• and
• a second emitter follower means coupled between said high and low rail conductors for programmably coupling data signals from said second data input to said second data output, provided said first emitter follower means is not simultaneously coupling data signals from said first data input to said second data output, said programmable coupling of said data signals from said second data input to said second data output carried out while applying a gain of approximately one or more to data signals propagating through said second emitter follower means while providing a desired amount of voltage level shifting of the signal levels propagating therethrough and a desired amount of additional current drive capacity over the current drive capacity of whatever circuit is driving said first data input.