Data processor

A data processor, comprising:

• a first data processing unit which has a plurality of arithmetic units and is used for reading an instruction from a first memory which stores a first group of instructions, and executing the instruction;
• a second data processing unit which has a plurality of arithmetic units capable of parallel operation and is used for executing instructions simultaneously executable as one instruction;
• a second memory for storing a second group of instructions executed by said second data processing unit,
• wherein when an instruction from said first group read by said first data processing unit is a predetermined instruction, an instruction from said second group is read from said second memory and executed by said second data processing unit;
• and
• a circuit for examining whether an operation of the instruction of the first instruction set executed subsequent to a branch to the instruction of the second instruction set is relevant to an operation of the instruction of the first instruction set which is restored after the execution of the instruction of the second instruction set, said microprocessor being capable of executing the instruction of the first instruction set at the restoring destination in parallel without waiting for the completion of the instruction of the second instruction set when no relevance exists.

A microprocessor, comprising:

• a reduced instruction set computer (RISC) core for executing a RISC instruction, a very long instruction word (VLIW) table for storing VLIW instructions, a VLIW core for executing a VLIW instruction, and a VLIW start decision unit for controlling operation switching between said RISC core and said VLIW core,
• wherein when said RISC core executes a subroutine call or a branch instruction out of RISC instructions, a VLIW instruction is read from said VLIW table by use of a branch destination address, operation is transferred by said VLIW start decision unit from said RISC core to said VLIW core, and said VLIW core is caused to operate until a VLIW instruction completion code is read from said VLIW table;
• and
• a circuit for examining whether an operation of the VLIW instruction executed subsequent to a branch to the VLIW instruction is relevant to an operation of the RISC instruction which is restored after the execution of the VLIW instruction, said microprocessor being capable of executing the RISC instruction at the restoring destination in parallel without waiting for the completion of the VLIW instruction when no relevance exists.

A microprocessor, comprising:

• a reduced instruction set computer (RISC) core for executing a RISC instruction, a very long instruction word (VLIW) table for storing VLIW instructions, a VLIW core for executing a VLIW instruction, and a VLIW start decision unit for controlling operation switching between said RISC core and said VLIW core,
• wherein when said RISC core executes a subroutine call or a branch instruction out of RISC instructions, a VLIW instruction is read from said VLIW table by use of a branch destination address, operation is transferred by said VLIW start decision unit from said RISC core to said VLIW core, and said VLIW core is caused to operate until a VLIW instruction completion code is read from said VLIW table;
• a register for storing information which is used to prohibit and control the execution of the VLIW instruction in a processor;
• and
• a function of lowering power consumption by causing a branch to a string of RISC instructions performing an operation equivalent to the VLIW instruction at the time execution of the VLIW instruction is prohibited so as to suspend the operation of the VLIW core.

A microprocessor, comprising:

• a reduced instruction set computer (RISC) core for executing a RISC instruction, a very long instruction word (VLIW) table for storing VLIW instructions, a VLIW core for executing a VLIW instruction, and a VLIW start decision unit for controlling operation switching between said RISC core and said VLIW core,
• wherein when said RISC core executes a subroutine call or a branch instruction out of RISC instructions, a VLIW instruction is read from said VLIW table by use of a branch destination address, operation is transferred by said VLIW start decision unit from said RISC core to said VLIW core, and said VLIW core is caused to operate until a VLIW instruction completion code is read from said VLIW table;
• and
• a register for storing information which is used to control the execution of VLIW instructions in the processor,
• wherein the execution of the VLIW instruction is prohibited if said register stores information for prohibiting the execution of the VLIW instruction.

A microprocessor, comprising:

• a reduced instruction set computer (RISC) core for executing a RISC instruction, a very long instruction word (VLIW) table for storing VLIW instructions, a VLIW core for executing a VLIW instruction, and a VLIW start decision unit for controlling operation switching between said RISC core and said VLIW core,
• wherein when said RISC core executes a subroutine call or a branch instruction out of RISC instructions, a VLIW instruction is read from said VLIW table by use of a branch destination address, operation is transferred by said VLIW start decision unit from said RISC core to said VLIW core, and said VLIW core is caused to operate until a VLIW instruction completion code is read from said VLIW table;
• and
• a register for storing information which is used to control the execution of VLIW instructions in the processor,
• wherein the execution of the VLIW instruction is prohibited and a plurality of RISC instructions equivalent to the VLIW instructions are executed if said register stores information for prohibiting the execution of the VLIW instructions.

A data processor, comprising:

• a first data processing unit which has a plurality of arithmetic units and is used for reading an instruction from a first memory which stores a first group of instructions, and executing the instruction;
• a second data processing unit which has a plurality of arithmetic units capable of parallel operation and is used for executing instructions simultaneously executable as one instruction;
• a second memory for storing a second group of instructions executed by said second data processing unit,
• wherein when an instruction from said first group read by said first data processing unit is a predetermined instruction, an instruction from said second group is read from said second memory and executed by said second data processing unit;
• and
• a register for storing information which is used to control the execution of the instruction of the second group of instructions in the processor,
• wherein the execution of the instruction of the second group of instructions in the processor is prohibited if said register stores information prohibiting the execution of the instruction of the second group of instructions in the processor.

A data processor, comprising:

• a first data processing unit which has a plurality of arithmetic units and is used for reading an instruction from a first memory which stores a first group of instructions, and executing the instruction;
• a second data processing unit which has a plurality of arithmetic units capable of parallel operation and is used for executing instructions simultaneously executable as one instruction;
• a second memory for storing a second group of instructions executed by said second data processing unit,
• wherein when an instruction from said first group read by said first data processing unit is a predetermined instruction, an instruction from said second group is read from said second memory and executed by said second data processing unit;
• and
• a register for storing information which is used to control the execution of the instruction of the second group of instructions in the processor,
• wherein the execution of the instruction of the second group of instructions in the processor is prohibited and a plurality of the instructions of the first set of instructions equivalent to the instruction of the second group of instructions are executed if said register stores information prohibiting the execution of the instruction of the second group of instructions in the processor.

A data processor comprising:

• a first processor;
• a second processor;
• wherein when said first processor executes a predetermined instruction of a first instruction set, said second processor executes an instruction of a second instruction set different from said first instruction set;
• and
• a register for storing information which is used to control the execution of the instruction of the second group of instructions in the processor,
• wherein the execution of the instruction of the second group of instructions in the processor is prohibited if said register stores information prohibiting the execution of the instruction of the second group of instructions in the processor.

A data processor comprising:

• a first processor;
• a second processor;
• wherein when said first processor executes a predetermined instruction of a first instruction set, said second processor executes an instruction of a second instruction set different from said first instruction set;
• and
• a register for storing information which is used to control the execution of the instruction of the second group of instructions in the processor,
• wherein the execution of the instruction of the second group of instructions in the processor is prohibited and a plurality of the instructions of the first set of instructions equivalent to the instruction of the second group of instructions are executed if said register stores information prohibiting the execution of the instruction of the second group of instructions in the processor.