Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array

A bit line hierarchy structure for a plurality of memory sub-arrays, comprising:

• a plurality of first hierarchy bit lines, each first hierarchy bit line being associated with a given memory sub-array of the plurality of memory sub-arrays;
• a plurality of second hierarchy bit lines, each second hierarchy bit line being associated with a different respective grouping of memory sub-arrays of the plurality of memory sub-arrays, each second hierarchy bit line partially overlapping at least one other second hierarchy bit line wherein the respective groupings of memory sub-arrays of said each second hierarchy bit line and said one other second hierarchy bit line share a common memory sub-array;
• and
• selective multiplexer means provided with each memory sub-array for selectively coupling said each memory sub-array to at least one of its associated first and second hierarchy bit lines.