Process for manufacturing solder leads on a semiconductor device package

A method of forming a packaged integrated circuit comprising:

• providing a silicon substrate;
• forming at least one metal layer onto said silicon substrate including a plurality of pads;
• providing a discrete packaging layer;
• aperturing the discrete packaging layer to provide an apertured discrete packaging layer having apertures located in locations corresponding to locations of said plurality of pads;
• attaching said apertured discrete packaging layer over said at least one metal layer so that said apertures communicate with said pads;
• forming a plurality of solder leads on an exterior surface of said at least one packaging layer;
• and
• forming electrical connections directly from individual ones of said plurality of pads to individual ones of said solder leads.