Method and apparatus for providing a signed integer divide by a power of two
AssigneeIntel Corporation
InventorRichard L. Maliszewski
Life of this patent
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Abstract
A method and apparatus to divide a signed integer by a constant power of two using conditionally-executed instructions to choose between a first result in the event that the dividend is a negative signed integer and a second result in the event that the dividend is a positive signed integer, wherein values associated with the first result and the second result are generated simultaneously.
Claims34
A machine-implemented method for dividing a signed integer by a constant power of two, said method comprising:
- providing an input number (R0), which comprises a signed integer, to be divided;
- simultaneously producing a first result (R1) pertaining to a case wherein R0 is negative input number, producing an associated conditionally executed instruction configured to transmit the first result as the final result if the input number is negative, and producing a second result (R2) pertaining to a case wherein R0 is a positive number;
- and
- if the input number is negative, executing the instruction.
A method of dividing a signed integer by a constant power of two comprising:
- providing an input number (R0) to be divided;
- providing a dividing factor (N) for the signed integer;
- in a first clock cycle:
- producing a first result (R1) pertaining to a negative input number where R1=R0+((2.sub.N)-1);
- producing a qualifying predicate for an instruction that shifts R1 by N to provide a final result (R3) and transmits the first result as a final result if the input number R0 is negative;
- and
- producing a second result (R2) pertaining to a positive number by executing an arithmetic right-shift of the input number R0 by N.
A computer system comprising:
- a microprocessor;
- and
- a compiler to compile instructions to divide a signed integer by a constant power of two in two clock cycles using instructions having qualifying predicates, the compiler including:
- a first input to receive an input number (R0) to be divided;
- a second input to receive a dividing factor (N) for the signed integer;
- a divider to simultaneously produce a first result (R1) pertaining to a negative input number, to produce an associated conditionally executed instruction to transmit the first result as a final result if the input number is negative and to produce a second result (R2) pertaining to a positive input number;
- and
- a qualifier to execute the instruction if the input number is negative.
A mechanism to divide a signed integer by a constant power of two and said mechanism comprising:
- a first input to receive an input number (R0) to be divided;
- a second input to receive a dividing factor (N) for the signed integer;
- a divider to simultaneously generate a first result (R1) pertaining to a negative input number, an associated conditionally executed instruction configured to transmit the first result as a final result if the input number is negative, and a second result (R2) pertaining to a positive input number;
- and
- a qualifier to execute the conditionally executed instruction if the input number is negative.
A method for dividing a signed binary number, said method comprising:
- generating in parallel a first value for said signed binary number, said first value representing a first modification of said signed binary number, and generating a second value representing a second modification of said signed binary number;
- determining whether said signed binary number is positive or negative;
- selecting a result associated with one of said first and second values, based on determining whether said signed binary number is positive or negative;
- and
- storing said result.
A computer-readable medium having stored thereon a set of processor-executable instructions, which, when executed by a processor, cause said processor to perform a method for dividing a signed binary number, said method comprising:
- generating in parallel a first value for said signed binary number, said first value representing a first modification of said signed binary number, and generating a second value representing a second modification of said signed binary number;
- determining whether said signed binary number is positive or negative;
- selecting a result associated with one of said first and second values, based on determining whether said signed binary number is positive or negative;
- and
- storing said selected result.
A computer system comprising:
- a memory device;
- a bus coupled to the memory device;
- and
- a processor, said processor coupled to the bus,
- said processor generates in parallel a first value for said signed binary number, said first value representing a first modification of said signed binary number, and generates a second value representing a second modification of said signed binary number,
- said processor determines whether said signed binary number is positive or negative;
- and
- said processor selects a result associated with one of said first and second values, based on determining whether said signed binary number is positive or negative.
A computer-readable medium, having stored thereon a first set of instructions, the first set of instructions, which when executed by a processor, generate a second set of instructions through a compilation process, the second set of instructions, which when executed by the processor, cause said processor to perform a method comprising:
- generating in parallel a first value for said signed binary number, said first value representing a first modification of said signed binary number, and generating a second value representing a second modification of said signed binary number;
- determining whether said signed binary number is positive or negative;
- selecting a result associated with one of said first and second values, based on determining whether said signed binary number is positive or negative;
- and
- storing said selected result.
Dependencies are inferred from the claim text.