Dual instruction set architecture

A processing system comprising:

• a microprocessor integrated circuit for executing instructions of a first instruction set;
• and
• an interface circuit separate from said microprocessor integrated circuit for providing an interface to the microprocessor integrated circuit, said interface circuit comprising:
• an input interface for receiving instructions of a second instruction set, said second instruction set being a complex instruction set computer (CISC) instruction set,
• a translator circuit for receiving instructions of the second instruction set from the input interface and translating the received instructions of the second instruction set to associated instructions of the first instruction set, and
• an output interface over which the translated instructions of the first instruction set are transmitted to the separate microprocessor integrated circuit.

A method of executing instructions in a processing system, comprising:

• providing a microprocessor integrated circuit for executing instructions of a first instruction set;
• providing an interface circuit separate from said microprocessor integrated circuit;
• with the interface circuit, receiving instructions of a second instruction set, said second instruction set being a complex instruction set computer (CISC) instruction set;
• with the interface circuit, translating the received instructions of the second instruction set to associated instructions of the first instruction set;
• and
• transmitting the translated instructions of the first instruction set to the separate microprocessor integrated circuit.

An interface circuit for providing an interface to a separate microprocessor integrated circuit, said microprocessor integrated circuit executing instructions of a first instruction set and said interface circuit being separate from said microprocessor integrated circuit, said interface circuit comprising:

• an input interface for receiving instructions of a second instruction set;
• a translator circuit for receiving instructions of the second instruction set from the input interface and translating the received instructions of the second instruction set to associated instructions of the first instruction set;
• an output interface over which the translated instructions of the first instruction set are transmittable from the interface circuit to the separate microprocessor integrated circuit;
• a first instruction queue for storing a group of instructions of the first instruction set before said group of instructions of the first instruction set is translated;
• and
• a second translated instruction queue for storing a group of translated instructions of the first instruction set before said group of translated instructions is transmitted to the microprocessor integrated circuit.

A processing system comprising:

• a microprocessor integrated circuit for executing instructions of a first instruction set;
• and
• an interface circuit separate from said microprocessor integrated circuit for providing an interface to the microprocessor integrated circuit, said interface circuit comprising:
• an input interface for receiving instructions of a second instruction set,
• a translator circuit for receiving instructions of the second instruction set from the input interface and translating the received instructions of the second instruction set to associated instructions of the first instruction set,
• an output interface over which the translated instructions of the first instruction set are transmittable to the separate microprocessor integrated circuit,
• a first instruction queue for storing a group of instructions of the first instruction set before said group of instructions of the first instruction set is translated;
• and
• a second translated instruction queue for storing a group of translated instructions of the first instruction set before said group of translated instructions is transmitted to the microprocessor integrated circuit.

A method executing instructions in a processing system, comprising:

• providing a microprocessor integrated circuit for executing instructions of a first instruction set;
• providing an interface circuit separate from said microprocessor integrated circuit;
• with the interface circuit, receiving instructions of a second instruction set;
• with the interface circuit, translating the received instructions of the second instruction set to associated instructions of the first instruction set;
• transmitting the translated instructions of the first instruction set to the separate microprocessor integrated circuit;
• providing a first instruction queue for storing a group of instructions of the first instruction set before said group of instructions of the first instruction set is translated;
• and
• providing a second translated instruction queue for storing a group of translated instructions of the first instruction set before said group of translated instructions is transmitted to the microprocessor integrated circuit.

A processing system comprising:

• a microprocessor integrated circuit for executing instructions of a first instruction set;
• and
• an interface circuit separate from said microprocessor integrated circuit for providing an interface to the microprocessor integrated circuit during the execution of the first instruction set by the microprocessor integrated circuit, said interface circuit comprising:
• an input interface for receiving instructions of a second instruction set;
• a translator circuit for receiving instructions of the second instruction set from the input interface and temporarily storing said second instruction set before translating the stored instructions of the second set to associated instructions of the first instruction set;
• and
• a memory, responsive to the translator circuit for temporarily storing the translated instructions and transmitting the translated instructions to an output interface over which the translated instructions are transmitted to the separate microprocessor integrated circuit.