Back to results
US 6,021,469 AGranted
Hardware virtual machine instruction processor
AssigneeSun Microsystems, Inc.
InventorsMarc Tremblay, James Michael O'Connor, William N. Joy
Life of this patent
Estimating the term…
Abstract
A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.
Claims10
A hardware virtual machine instruction processor comprising:
- a virtual machine instruction cache unit including:
- an instruction cache;
- and
- an instruction buffer coupled to said virtual machine instruction cache to receive a virtual machine instruction;
- a virtual machine instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction;
- an integer unit coupled to said virtual machine instruction decode unit wherein said integer unit executes integer instructions;
- and
- a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises:
- a stack cache;
- and
- a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache.
8 more elements
A hardware virtual machine instruction processor comprising:
- an instruction cache unit including:
- an instruction cache;
- and
- an instruction buffer coupled to said instruction cache to receive a virtual machine instruction;
- an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction;
- an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions;
- a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises:
- a stack cache;
- and
- a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache;
- and
- a method argument cache coupled to an instruction decoder in said instruction decode unit.
9 more elements
A hardware virtual machine instruction processor comprising:
- an instruction cache unit including:
- an instruction cache, and
- an instruction buffer coupled to said instruction cache to receive a virtual machine instruction;
- an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction;
- an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions;
- a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises:
- a stack cache;
- and
- a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache;
- and
- a local variable look-aside cache in said stack management unit.
8 more elements
A hardware virtual machine instruction processor comprising:
- an instruction cache unit including:
- an instruction cache;
- and
- an instruction buffer coupled to said instruction cache to receive a virtual machine instruction;
- an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction;
- an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions;
- a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises:
- a stack cache;
- and
- a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache;
- and
- a getfield-putfield acceleration unit coupled to said integer unit.
9 more elements
A hardware virtual machine instruction processor comprising:
- an instruction cache unit including:
- an instruction cache;
- and
- an instruction buffer coupled to said instruction cache to receive a virtual machine instruction;
- an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction;
- an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions;
- a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises:
- a stack cache;
- and
- a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache;
- and
- a lookup-switch acceleration unit coupled to said integer unit.
9 more elements
A hardware virtual machine instruction processor comprising:
- an instruction cache unit including:
- an instruction cache;
- and
- an instruction buffer coupled to said instruction cache to receive a virtual machine instruction;
- an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction;
- an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions;
- a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises:
- a stack cache;
- and
- a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache;
- and
- a bounds check unit coupled to said integer unit.
9 more elements
A hardware virtual machine instruction processor comprising:
- an instruction cache unit including:
- an instruction cache;
- and
- an instruction buffer coupled to said instruction cache to receive a virtual machine instruction;
- an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction;
- an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions;
- a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises:
- a stack cache;
- and
- a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache;
- and
- a memory allocation accelerator in a data cache unit coupled to said dribble management unit.
9 more elements
Dependencies are inferred from the claim text.