Integrated relay ladder language, reduced instruction set computer

An integrated circuit electronic computer comprising:

• address and data lines connectable to memory for exchanging data on the data lines at a memory address corresponding to an address on the address lines;
• instruction decoding circuit attached to the data lines for receiving an instruction therefrom and providing decoded instruction signals;
• a plurality of storage registers communicating with the address and data lines and the instruction decoding circuit to receive and transmit data from and to the data lines;
• an arithmetic/logic/relay ladder unit connected to the storage registers, the data lines, and the instruction decoding circuit for receiving data from at least one register to operate on that data, according to an instruction signal, to produce an output;
• wherein the arithmetic/logic/relay ladder unit operates on the data according to different instruction signals to execute arithmetic instructions, logic instructions and relay ladder instructions;
• wherein the instruction decode circuitry may communicate an instruction signal to a register causing the register to conditionally provide data to the data lines for storage in the external memory based on the output of the arithmetic/logic/relay ladder unit from an earlier relay ladder instruction.

An integrated circuit electronic computer comprising:

• address and data lines connectable to memory for exchanging data on the data lines at a memory address corresponding to an address on the address lines;
• instruction decoding circuit attached to the data lines for receiving an instruction therefrom and providing decoded instruction signals;
• a plurality of storage registers communicating with the address and data lines and the instruction decoding circuit to receive and transmit data from and to the data lines;
• an arithmetic/logic/relay ladder unit connected to the storage registers, the data lines, and the instruction decoding circuit for receiving data from at least one register to operate on that data, according to an instruction signal, to produce an output;
• wherein the arithmetic/logic/relay ladder unit operates on the data according to different instruction signals to execute arithmetic instructions, logic instructions and relay ladder instructions;
• including first and second condition code registers having flags set by the operation of the arithmetic instructions, wherein the arithmetic instructions may be designated to change the flags of the first condition code register only.