Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability
AssigneeTexas Instruments Incorporated
InventorAnthony Bessios
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Abstract
Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n.gtoreq.5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.
Claims24
A method for modulating a predefined number of bits of a binary data word X.sub.n with a predetermined set of target constraints into codewords having a predefined number of code bits C.sub.n+1 bits comprising the steps of:
- a. pad the data word [X.sub.n =x.sub.1 x.sub.2 . . . x.sub.n ] with zeros to the form [0 x.sub.1 x.sub.2 . . . x.sub.n 0],
- b. process the padded data word with 1.sym.D to form the pre-encoded codeword C'.sub.n+1 such that all C'.sub.n+1 have even weight;
- and
- c. choose the pre-encoded codewords C'.sub.n+1 which violate a target constraint and invert in a decodable way an odd number of bits of the codeword to form the odd parity codeword C.sub.n+1 which satisfies the target constraints.
A method for RLL coding a predefined number of bits of a binary data word X.sub.n with predetermined target constraints into codewords having a predefined number of code bits C.sub.n+1 comprising the steps of:
- a. pad the data word X.sub.n =[x.sub.1 x.sub.2 . . . x.sub.n ] with zeros to the form [0 x.sub.1 x.sub.2 . . . x.sub.n 0],
- b. process the padded data word with 1.sym.D to form the pre-encoded codeword C'.sub.n+1 ;
- and
- c. choose the pre-encoded codewords which violate a target constraint and invert an odd number of bits of the codeword to form the codeword C.sub.n+1 so that said target constraints are satisfied.
A computer hard disk drive having a digital communications system which modulates a predefined number of bits of a binary data word X.sub.n with a predetermined set of target constraints into codewords having a predefined number of code bits C.sub.n+1 bits comprising:
- a. a convolution circuit for processing the padded data word of the form [0 X.sub.n 0], with 1.sym.D to form the pre-encoded codeword C'.sub.n+1 ;
- and
- b. a inversion circuit which inverts an odd number of bits of the any codewords which violate a target constraint to form the codeword C.sub.n+1.
Dependencies are inferred from the claim text.