Test system with mechanical alignment for semiconductor chip scale packages and dice

A test system for semiconductor components comprising:

• a semiconductor component comprising a plurality of contact bumps and an alignment member;
• an interconnect comprising a plurality of indentations covered with conductive layers, the indentations configured to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations;
• and
• an alignment fixture comprising a polymer layer on the interconnect comprising an opening with a surface for engaging the alignment member to align the contact bumps with the indentations.

A test system for semiconductor components comprising:

• a component comprising a plurality of contact bumps in a arid array and at least one alignment member;
• a base configured to retain the component comprising a plurality of external contacts connectable to test circuitry;
• an interconnect on the base comprising a plurality of contact members in electrical communication with the external contacts on the base, the contact members comprising indentations configured to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations;
• and
• an alignment fixture on the interconnect comprising a surface configured to engage the alignment member on the component to align the contact bumps to the contact members.

A method for fabricating a test system for semiconductor components comprising:

• providing a component comprising a plurality of external contact bumps and an alignment member;
• providing an interconnect comprising a plurality of contact members configured to make temporary electrical connections with the contact bumps, each contact member comprising an indentation at least partially covered with a conductive layer and configured to retain and electrically contact a contact bump, the indentation comprising a sloped sidewall configured to guide the contact bump into the indentation;
• and
• forming an alignment fixture by depositing a polymer layer on the interconnect having a surface configured to engage the alignment member to align the contact bumps to the contact members.

A method for fabricating a test system for semiconductor components comprising:

• providing a component comprising a plurality of contact bumps and an alignment member;
• providing an interconnect comprising a plurality of contact members configured to make temporary electrical connection with the contact bumps, the contact members comprising indentations at least partially covered with conductive layers, the indentations sized to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations;
• forming a resist layer on the interconnect;
• forming a surface on the resist layer configured to contact the alignment member to align the component with the interconnect;
• and curing the resist layer.