Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions

A semiconductor memory device comprising:

• an SOI substrate;
• a plurality of word lines disposed in a row direction on said SOI substrate;
• and
• a plurality of first blocks formed on said SOI substrate, wherein
• each of said plurality of first blocks includes
• first and second bit line pairs disposed in a column direction,
• a plurality of memory cells each provided correspondingly to any one of crossings between said plurality of word lines and said first and second bit line pairs, and each including a capacitor and a first transistor connected between said capacitor and one of the bit lines in the corresponding bit line pair and being turned on in response to a potential of the corresponding word line,
• a first sense amplifier provided correspondingly to said first bit line pair and connected to said first bit line pair, and
• a second sense amplifier provided correspondingly to said second bit line pair and connected to said second bit line pair;
• one of the bit lines in said first bit line pair is disposed between one and the other of the bit lines in said second bit line pair;
• one of the bit lines in said second bit line pair is disposed between one and the other of the bit lines in said first bit line pair;
• each of said plurality of first blocks further includes a first body fixing line disposed at one side of one portion of one bit line in said first bit line pair, and supplied with a fixed potential,
• a second body fixing line disposed at the other side of the other portion of the one bit line in said first bit line pair, and supplied with said fixed potential,
• a third body fixing line disposed at one side of one portion of one bit line in said second bit line pair, and supplied with said fixed potential, and
• a fourth body fixing line disposed at the other side of the other portion of the one bit line in said second bit line pair, and supplied with said fixed potential;
• each of said first transistors in said plurality of memory cells includes a source region, a drain region and a body region located between said source and drain regions;
• and
• said body regions of said first transistors of said plurality of memory cells are connected to said first to fourth body fixing lines.

A semiconductor memory device comprising:

• an SOI substrate:
• a plurality of blocks disposed in a first direction on said SOI substrate;
• and
• a plurality of main bit line pairs formed in a first layer and disposed in columns each extending along the first direction across said plurality of blocks, wherein
• each of said plurality of blocks includes
• a plurality of sub-bit line pairs formed in a second layer different from said first layer, each provided correspondingly to one main bit line pair among said plurality of main bit line pairs and each extending along said one main bit line pair,
• a plurality of switching means for being turned on in response to a predetermined block select signal, each of said switching means being provided correspondingly to one sub-bit line in said plurality of sub-bit line pairs, and being connected between the corresponding sub-bit line and one main bit-line in the corresponding main bit line pair,
• a plurality of word lines disposed in rows each extending along a second direction crossing to the first direction, and
• a plurality of memory cells provided correspondingly to crossings between said plurality of sub-bit line pairs and said plurality of word lines, each of said plurality of memory cells including a capacitor and a first transistor connected between said capacitor and one sub-bit line in the corresponding sub-bit line pair and being turned on in response to the potential of the corresponding word line, said semiconductor memory device further comprising
• a plurality of body fixing lines formed in said second layer and applied with a fixed potential, and each disposed between the plurality of sub-bit lines corresponding to one of said plurality of main bit line pairs and the plurality of sub-bit line pairs corresponding to another main bit line pair adjacent to said one main bit line pair;
• wherein
• said first transistors in said plurality of memory cells each includes a source region, a drain region and a body region located between said source and drain regions;
• and
• said body regions of said first transistors in said plurality of memory cells are connected to said plurality of body fixing lines.

A semiconductor memory device comprising:

• an SOI substrate;
• a plurality of word lines disposed in rows on said SOI substrate;
• a plurality of bit line pairs disposed in columns on said SOI substrate;
• a plurality of memory cells disposed on said SOL substrate and corresponding to crossings between said plurality of word lines and said plurality of bit line pairs;
• a plurality of sense amplifiers disposed on said SOI substrate and connected to said plurality of bit line pairs, respectively, each including first and second transistors cross-coupled with each other, said first and second transistors each having a source region, a drain region and a body region located between said source region and said drain region;
• and
• a first body fixing line disposed on said SOI substrate, supplied with a first fixed potential and connected to said body regions of said first and second transistors.

A semiconductor memory device, comprising:

• an SOI substrate;
• a plurality of word lines disposed in rows on said SOI substrate;
• a plurality of bit line pairs disposed in columns direction on said SOI substrate;
• a plurality of memory cells disposed on said SOI substrate and corresponding to crossings between said plurality of word lines and said plurality of bit line pairs;
• a sense amplifier driving line disposed on said SOI substrate;
• a power supply line disposed on said SOI substrate;
• a driver transistor disposed on said SOI substrate, connected between said sense amplifier driving line and said power supply line, and turned on in response to a drive signal;
• and
• a plurality of sense amplifiers disposed on said SOI substrate and connected to said plurality of bit line pairs, respectively, each including first and second transistors cross-coupled with each other, said first and second transistors each having a source region connected to said sense amplifier driving line, a drain region, and a body region located between said source region and said drain region and connected to said sense amplifier driving line.

A semiconductor memory device, comprising:

• an SOI substrate;
• a bit line pair disposed on said SOI substrate;
• a body fixing line disposed on said SO substrate and supplied with a fixed potential;
• a sense amplifier disposed on said SOI substrate, connected to said bit line pair and including first and second transistors cross-coupled with each other, said first and second transistors each having a gate electrode, a source region, a drain region and a body region underlying said gate electrode and located between said source region and said drain region, said body region extending beyond said gate electrode and connected to said body fixing line.

A semiconductor memory device comprising:

• an SOI substrate;
• a bit line pair disposed on said SOI substrate;
• a precharge transistor disposed on said SOI substrate and connected to one bit line of said bit line pair, said precharge transistor having a source region, a drain region and a body region located between said source region and said drain region;
• an equalize transistor disposed on said SOI substrate and connected between one and the other bit lines of said bit line pair, said equalize transistor having a source region, a drain region, and a body region located between said source region and said drain region and extending to said body region of said precharge transistor;
• a sense amplifier disposed on said SOI substrate, connected to is said bit line pair and including first and second transistors cross-coupled with each other, said first transistor having a source region, a drain region, and a body region located between said source region and said drain region and extending to said body region of said equalize transistor;
• and
• a body fixing line disposed on said SOI substrate between said equalize transistor and said sense amplifier, supplied with a fixed potential, and connected to said body region of said precharge transistor, said body region of said equalize transistor and said body region of said first transistor.

A semiconductor memory device comprising:

• an SOI substrate;
• a bit line pair disposed on said SOI substrate;
• a sense amplifier driving line disposed on said SOI substrate;
• a power supply line disposed on said SOI substrate;
• a driver transistor disposed on said SOI substrate, connected between said sense amplifier driving line and said power supply line, and turned on in response to a drive signal;
• and
• a sense amplifier disposed on said SOI substrate and connected to said bit line pair, including first and second transistors cross-coupled with each other, said first transistor having a source region, a drain region, and a body region located between said source region and said drain region and connected to said source region, said second transistor having a source region also serving as the source region of said first transistor, a drain region, and a body region located between said source region and said drain region and connected to said source region, said region serving as said first transistor source region and said second transistor source region being connected to said sense amplifier driving line.

A semiconductor memory device comprising:

• an SOI substrate;
• a plurality of word lines disposed in rows on said SOI substrate;
• a plurality of bit line pairs disposed in columns on said SOI substrate;
• a plurality of body fixing lines disposed on said SOI substrate and supplied with a fixed potential, each disposed between two adjacent bit line pairs of said plurality of bit line pairs;
• and
• a plurality of memory cells disposed on said SOI substrate and corresponding to crossings between said plurality of word lines and said plurality of bit line pairs, each including an access transistor having a source region, a drain region and a body region located between said source region and said drain region, said body region extending under one body fixing line of said plurality of body fixing lines and connected to said one body fixing line.

A semiconductor memory device comprising:

• an SOI substrate;
• a plurality of word lines disposed in rows on said SOI substrate;
• a plurality of bit line pairs disposed in columns on said SOI substrate;
• a plurality of body fixing lines disposed on said SOI substrate and supplied with a fixed potential, each disposed between two adjacent bit line pairs of said plurality of bit line pairs;
• a plurality of memory cells disposed on said SOI substrate and corresponding to crossings between said plurality of word line and said plurality of bit line pairs, each including an access transistor having a source region, a drain region and a body region located between said source region and said drain region and a body region located between said source region and said drain region, a body region of an access transistor of one memory cell corresponding to a bit line pair disposed closer to one side of one body fixing line of said plurality of body fixing lines extending under said one body fixing line to a body region of an access transistor of one memory cell corresponding to a bit line pair disposed closer to the other side of said one body fixing line of said plurality of body fixing lines and being connected to said one body fixing line.

A semiconductor memory device comprising;

• an SOI substrate;
• a plurality of word lines disposed in rows on said SOI substrate;
• a plurality of bit line pairs disposed in columns direction on said SOI substrate;
• a plurality of body fixing lines disposed on said SOI substrate and supplied with a fixed potential, each disposed between two adjacent bit line pairs of said plurality of bit line pairs;
• and
• a plurality of memory cells disposed on said SOI substrate and corresponding to crossings between said plurality of word lines and said plurality of bit line pairs, each including an access transistor having a source region, a drain region and a body region located between said source region and said drain region, body regions of access transistors of two memory cells corresponding to a bit line pair disposed closer to one side of one body fixing line of said plurality of body fixing lines extending under said one body fixing line to body regions of access transistors of two memory cells corresponding to a bit line pair disposed closer to the other side of said one body fixing line of said plurality of body fixing lines and being connected to said one body fixing line.