Software pipelining a hyperblock loop
AssigneeIntel Corporation
InventorPohua Chang
Life of this patent
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AssigneeIntel Corporation
InventorPohua Chang
Estimating the term…
An iterative software pipelining method promotes instructions of a program loop to previous loop iterations and then reschedules the instructions until either 1) the resultant schedule is optimal (i.e., the initiation interval is equal to the minimal initiation interval) or 2) the resultant schedule is not an improvement over the previous schedule generated. The method is applicable to a sequence of instructions within a program loop having a single control flow entry and one or more control flow exit points. First, a minimum initiation interval of the program loop is computed. Second, instruction level parallelism transformations are applied on the program loop. Third, a single iteration schedule is determined for the program loop. Fourth, selected instructions are percolated to a prior iteration of the program loop to generate a new instruction order for the program loop. Each of steps two through four is performed as long as a previous length of the program loop exceeds a single iteration schedule length and the single iteration schedule length exceeds the minimum initiation interval.
A machine-readable medium having stored thereon sequences of instructions that when executed by a processor cause the processor to:
A machine-readable medium having stored thereon sequences of instructions that when executed by a processor cause the processor to:
A machine-readable medium having stored thereon sequences of instructions that when executed cause the processor to:
An apparatus comprising:
An apparatus comprising:
An apparatus comprising:
A system comprising:
A system comprising:
A system comprising:
Dependencies are inferred from the claim text.