Clock vernier adjustment

A signal coupling system, comprising:

• a memory controller generating a clock signal on a clock terminal and a plurality of bits of a digital signal on a signal bus;
• a vernier clock adjustment circuit having a clock input coupled to the clock terminal of the memory controller to receive the clock signal from the memory controller, the vernier clock adjustment circuit providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay, the vernier clock adjustment circuit further having a delay adjustment input adapted to receive delay control signals controlling the magnitude of the rising-edge delay and the falling-edge delay;
• and
• a plurality of latches, each latch having an input terminal coupled to a respective bit of the signal bus and first and second clock terminals coupled to the vernier clock adjustment circuit to receive the rising-edge clock signal and the falling-edge clock signal, the latches being constructed to store respective bits of the digital signal from the memory controller on the rising-edge of the rising-edge clock signal and on the falling-edge of the falling-edge clock signal.

A signal coupling system, comprising:

• a memory controller generating a clock signal on a clock terminal and receiving or supplying a plurality of bits of a digital signal on a signal bus;
• a vernier clock adjustment circuit having a clock input coupled to the clock terminal of the memory controller to receive the clock signal from the memory controller, the vernier clock adjustment circuit providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay, the vernier clock adjustment circuit further having a delay adjustment input adapted to receive delay control signals controlling the magnitude of the rising-edge delay and the falling-edge delay;
• and
• a plurality of First-In, First-Out ("FIFO") buffers, each having an input terminal coupled to a respective bit of the signal bus and first and second clock terminals coupled to the vernier clock adjustment circuit to receive the rising-edge clock signal and the falling-edge clock signal, the FIFO buffers being constructed to receive respective bits of the digital signal from the memory controller or supply respective bits of the digital signal to the memory controller on the rising-edge of the rising-edge clock signal and on the falling-edge of the falling-edge clock signal.

A memory device comprising:

• a data bus coupling data to and from the memory device;
• a plurality of arrays of memory cells for storing data, the arrays of memory cells including a data path coupling data to and from the data bus;
• a command bus receiving commands to generate control signals corresponding thereto;
• a clock line receiving an input clock signal;
• and
• a vernier clock adjustment circuit receiving the input clock signal, the vernier clock adjustment circuit including a rising-edge delay circuit receiving the input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay, the vernier clock adjustment circuit further including a falling-edge delay circuit receiving the rising-edge clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay;
• and
• an edge triggered circuit receiving the rising-edge clock signal and the falling-edge clock signal, the edge triggered circuit performing a predetermined operation in the memory device at a first edge of the rising-edge clock signal and at a second edge of the falling-edge clock signal.

A memory device comprising:

• a data bus coupling data to and from the memory device;
• a plurality of arrays of memory cells for storing data, the arrays of memory cells including a data path coupling data to and from the data bus;
• a command bus receiving commands to generate control signals corresponding thereto;
• a clock line receiving an input clock signal;
• and
• a vernier clock adjustment circuit receiving the input clock signal, the vernier clock adjustment circuit including a falling-edge delay circuit receiving the input clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay, the vernier clock adjustment circuit further including a rising-edge delay circuit receiving the falling-edge clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay;
• and
• an edge triggered circuit receiving the rising-edge clock signal and the falling-edge clock signal, the edge triggered circuit performing a predetermined operation in the memory device at a first edge of the falling-edge clock signal and at a second edge of the rising-edge clock signal.

A method of operating an integrated circuit, comprising:

• receiving an input clock signal;
• delaying the input clock signal by a rising-edge delay to provide a rising-edge clock signal;
• delaying the rising-edge clock signal by a falling-edge delay to provide a falling-edge clock signal;
• performing a first operation on the binary signal at a first edge of the rising-edge clock signal;
• and
• performing a second operating at a second edge of the falling-edge clock signal.

A method of operating an integrated circuit, comprising:

• receiving an input clock signal;
• delaying the input clock signal by a falling-edge delay to provide a falling-edge clock signal;
• delaying the falling-edge clock signal by a rising-edge delay to provide a rising-edge clock signal;
• performing a first operation on the binary signal at a first edge of the falling-edge clock signal;
• and
• performing a second operating at a second edge of the rising-edge clock signal.

A method of operating an integrated circuit, comprising:

• receiving an input clock signal;
• generating a first trigger signal subsequent to each rising-edge of the input clock signal, each first trigger signal being generated after a rising-edge delay has elapsed from each rising-edge of the input clock signal;
• generating a second trigger signal subsequent to each falling-edge of the input clock signal, each second trigger signal being generated after a falling-edge delay has elapsed from each falling-edge of the input clock signal;
• and
• performing a predetermined operation on the binary signal responsive to each of the first and second trigger signals.

A method of operating an integrated circuit, comprising:

• receiving an input clock signal;
• establishing a rising-edge delay value;
• establishing a falling-edge delay value;
• performing a first operation in the integrated circuit after a first delay has elapsed from each rising-edge of the input clock signal, the first delay corresponding to the rising-edge delay value;
• and
• performing a second operation in the integrated circuit after a second delay has elapsed from each falling-edge of the input clock signal, the second delay corresponding to the falling-edge delay value.

A method of operating an integrated circuit, comprising:

• receiving an input clock signal;
• establishing a falling-edge delay value;
• establishing a rising-edge delay value;
• performing a first operation in the integrated circuit after a first delay has elapsed from each falling-edge of the input clock signal, the first delay corresponding to the falling-edge delay value;
• and
• performing a second operation in the integrated circuit after a second delay has elapsed from each rising-edge of the input clock signal, the second delay corresponding to the rising-edge delay value.