Data processing circuit with self-timed instruction execution and power regulation

A data processing circuit, comprising

• a self timed instruction execution unit having an interface for transmitting a ready signal and for receiving a request signal, the instruction execution unit generating the ready signal to indicate readiness to start executing a first instruction, the instruction execution unit starting execution of the first instruction upon receiving the request signal;
• a sequencing unit coupled to the interface, for generating the request signal in response to the ready signal, said sequencing unit generates a predetermined first number of further request signals and transmits said further request signals to the instruction execution unit upon receiving corresponding further ready signals to execute a corresponding predetermined number of intermediate instructions between a start of execution of the second instruction, whose execution precedes execution of the first instruction, and generating the request signal for starting execution of the first instruction;
• a timer for timing a predetermined time-interval starting with the execution of a second instruction and generating the request signal for starting execution of the first instruction, the timer being coupled to the sequencing unit for disabling transmission of the request signal to the instruction execution unit for starting execution of the first instruction until after the time-interval has elapsed;
• a counter coupled to the sequencing unit for counting a second number of intermediate instructions that the instruction execution unit starts executing after the second instruction, wherein the counter disables said transmission of said further request signals to the execution unit to execute said intermediate instructions when said second number has reached the predetermined first number.