US 6,014,682 A · Methods and apparatus for variable-rate down-sampling filters for discrete-time sampled systems using a fixed sampling rate

Abstract

Methods and apparatus for variable-rate down-sampling filters for discrete-time sampled systems using a fixed sampling rate are disclosed. The Variable Rate Down-Sampling Filter allows a continuous range of sample rates to be derived from input samples at a fixed rate. The output rate does not have to be related to the fixed input rate in any integral or rational way, and in fact, the output rate can vary in time such as will occur when tracking a signal received from a station using a different timebase. A fixed sampling rate at the A/D Converter greatly simplifies the design of the analog front end. A single anti-aliasing filter can be designed and precisely matched to the fixed sampling rate. Used with a frequency-modulated numerically controlled oscillator (NCO), the Down-Sampling Filter keeps the entire frequency-synthesis and time-tracking loop in the digital domain. The need for an analog time-tracking loop to adjust the sampling instant at the A/D converter is eliminated. The need for an analog frequency synthesizer to generate a variable sampling rate is also eliminated. System design and performance analysis are simplified as well by eliminating the complication of hybrid analog-digital control loops. Details are disclosed.

Claims31

Dependent claims

In a digital filter, the improvement comprising:

a W bit wide register having a register input, a register output and a sample clock input;
a W bit wide first-adder having first and second first-adder inputs, a first-adder output and a carry output;
a coefficient generator having an address input and a plurality of multi-bit filter coefficient outputs;
the first first-adder input being coupled to receive a frequency word;
the first-adder output being coupled to the register input;
the register output being coupled to the address input of the coefficient generator and to the second first-adder input;
the register clock input being coupled to receive a sample clock signal;
the carry output being coupled to provide a shift control signal;
the address input of the coefficient generator is P bits wide, wherein P is less than W, and wherein only the P most significant bits of the register output are coupled to the address input of the coefficient generator, the coefficient generator storing M times 2.sup.P coefficients, M coefficients at each coefficient generator address;
and
a plurality M of multiplier-accumulator circuits, each multiplier-accumulator circuit being coupled to receive a respective one of each M filter coefficient outputs of the coefficient generator and a signal sample at the sample clock rate, multiply the same together and accumulate the results in an accumulator, the multiplier-accumulator circuits being coupled in series and responsive to a shift control input to shift the contents of each accumulator in the series of multiplier-accumulator circuits to the accumulator of the next multiplier-accumulator circuit, the contents of the accumulator of the last multiplier-accumulator circuit forming the multiplier-accumulator circuits' output.

8 more elements

In a digital filter, the improvement comprising:

a coefficient generator having a phase input and a plurality of filter coefficient outputs, the phase input of the coefficient generator being P bits wide, the coefficient generator producing M times 2.sup.P coefficients, M coefficients for each phase value;
a plurality M of multiplier-accumulator circuits, each multiplier-accumulator circuit being coupled to receive a respective one of each M filter coefficient outputs of the coefficient generator and a signal sample at a sample clock rate, multiply the same together and accumulate the results in an accumulator, the multiplier-accumulator circuits being coupled in series and responsive to a shift control input to shift the contents of each accumulator in the series of multiplier-accumulator circuits to the accumulator of the next multiplier-accumulator circuit, the contents of the accumulator of the last multiplier-accumulator circuit forming the multiplier-accumulator circuits' output.

A digital filter comprising:

a numerically controlled oscillator responsive to a clock signal and a numerical control signal to advance its count on each clock signal by an amount determined by the numerical control signal, the oscillator providing as outputs, the present oscillator count at every clock cycle and a rollover signal each time it counts through a predetermined count;
a coefficient generator having a phase input and a plurality of filter coefficient outputs, the phase input of the coefficient generator being P bits wide, the coefficient generator producing M times 2.sup.P coefficients, M coefficients for each phase value;
a plurality M of multiplier-accumulator circuits, each multiplier-accumulator circuit being coupled to receive a respective one of each M filter coefficient outputs of the coefficient generator and a signal sample at every clock cycle, multiply the same together and accumulate the results in an accumulator, the multiplier-accumulator circuits being coupled in series and responsive to the rollover signal to shift the contents of each accumulator in the series of multiplier-accumulator circuits to the accumulator of the next multiplier-accumulator circuit, the contents of the accumulator of the last multiplier-accumulator circuit forming the multiplier-accumulator circuits' output.

A method for variable-rate down-sampling filtering for discrete-time sampled systems using a fixed sampling rate comprising:

providing a numerically controlled oscillator responsive to a sample clock signal and a numerical control signal to advance its count on each clock signal by an amount determined by the numerical control signal, the oscillator providing as outputs, the present oscillator count at every sample clock and a rollover signal each time it counts through a predetermined count, the present oscillator count being P bits wide;
providing a coefficient generator having a phase input and a plurality of filter coefficient outputs, the phase input of the coefficient generator receiving the present oscillator count of the numerically controlled oscillator, the coefficient generator producing M times 2P coefficients, M coefficients for each phase input;
providing a plurality M of multiplier-accumulator circuits, each multiplier-accumulator circuit receiving a respective one of each M filter coefficient outputs of the coefficient generator and a signal sample at the sample clock rate, multipling the same together and accumulating the results in an accumulator, the multiplier-accumulator circuits being coupled in series and responsive to the rollover signal to shift the contents of each accumulator in the series of multiplier-accumulator circuits to the accumulator of the next multiplier-accumulator circuit, the contents of the accumulator of the last multiplier-accumulator circuit forming the multiplier-accumulator circuits' output.

Dependencies are inferred from the claim text.

Methods and apparatus for variable-rate down-sampling filters for discrete-time sampled systems using a fixed sampling rate

Life of this patent

Methods and apparatus for variable-rate down-sampling filters for discrete-time sampled systems using a fixed sampling rate

Life of this patent

Abstract

Claims31