US 6,014,043 AGranted

Current switching type switch circuit

AssigneeNEC Corporation

InventorYoshio Nishida

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Abstract

A current switching type switch circuit is constructed with a constant current source, a switch group consisted of a pair of P-type MOS transistors and a current mirror circuit consisted of first, second, third and fourth npn bipolar transistors. The sources of the P-type MOS transistors are connected in common and to a first power source via the constant current source. Complementary clock signals are input to the gates of the P-type MOS transistors. Collectors and bases of first and second npn bipolar transistors are respectively connected to drains of the P-type MOS transistors, and to bases of third and fourth npn bipolar transistors. Collectors of the third and fourth npn bipolar transistors are respectively connected to first and second load circuits. Also, emitters of all of npn bipolar transistors are connected to a second power source.

Claims10

Dependent claims

A current switching type switch circuit comprising:

a current source connected between a first power source line and a first node;
a first transistor connected between said first node and a second node, an non-inverting clock signal being supplied to a control terminal of said first transistor;
a second transistor connected between said first node and a third node, an inverting clock signal being supplied to a control terminal or said second transistor;
a third transistor being connected between said second node and a second power source line, a control terminal of said third transistor connected to said second nods;
a fourth transistor connected between a third node and said second power source line, a control terminal of said fourth transistor being connected to said third node;
a fifth transistor connected between said second power source line and a fourth node, a control terminal of said fifth transistor being connected to said second node, and a first load circuit being connected between said fourth node and said first power source line;
and
a sixth transistor connected between said second power source line and a fifth node, a control terminal of said sixth transistor being connected to said third node, a second load circuit being connected between said fifth node and said first power source line, said first and second load circuits being complimentarily driven in response to said non-inverting and inverting clock signals, respectively.

5 more elements

Dependencies are inferred from the claim text.