Apparatus and method for controlling data, address, and enable buses within a microprocessor

Abstract

A CPU includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU includes a decode stage, an arbitration stage, and a control stage. Incoming requests asserted by the CPU module unit are provided to the BIU decode stage which, in response thereto, determines the type of transaction requested, the initiator module unit, and the target module unit. If the target identified in the decoded request is ready to accept a command, the decode stage forwards the request to the arbitration stage. The arbitration stage arbritrates amoung the present requests asserted by the module units and, in response thereto, alerts the control stage as to which of the module units has won the arbitration. The control stage decodes the request corresponding to the module unit that won the arbitration to determine the transaction type and target unit. The control stage selects within appropriate address and data multiplexers those inputs corresponding to the initiator and target units identified in the request. In this manner, the dedicated buses between the initiator unit and the BIU are effectively coupled to the common bus so as to allow for the transmission of information from the initiator unit to the target unit via the BIU.

Dependencies are inferred from the claim text.