Back to results
US 6,011,734 AGranted
Fuseless memory repair system and method of operation
AssigneeMotorola, Inc.
InventorBernard J. Pappert
Life of this patent
Estimating the term…
Abstract
A Built-In Self Test (720) generates a BIST FAIL signal when a failure is detected at a specific address within a memory array (110). The address associated with the failure is stored in a latch (210). During normal operation, the address stored in latch (210) is compared to addresses being currently accesses. A HIT signal is generated when a match occurs. The HIT signal disables selection of the defective row in array (110). A redundant row select signal selects the redundant row (112) to replace the defective row.
Claims19
A semiconductor device comprising:
- a memory array having a plurality of rows;
- a built-in self test (BIST) portion for detecting a defective row within the memory array, and having an output node for providing a BIST FAIL signal, wherein the BIST FAIL signal is active for indicating the defective row is detected;
- a first row decoder coupled to the plurality of rows in the memory array;
- circuitry for latching an address of the defective row, the circuitry having an input node for receiving the BIST FAIL signal, wherein the address of the defective row is latched when the BIST FAIL signal is active;
- a plurality of redundant rows;
- a second row decoder coupled to the circuitry for latching and to the plurality of redundant rows;
- and
- a control circuit coupled to the plurality of redundant rows and to the first row decoder for preventing the first row decoder from enabling the defective row and replacing the defective row with a redundant row.
5 more elements
A semiconductor device comprising:
- a memory having a first bank and a second bank;
- the first bank of memory comprising:
- a first plurality of rows;
- a first row decoder for selecting one of the first plurality of rows;
- and
- a first redundant row;
- the second memory bank comprising:
- a second plurality of rows;
- a second row decoder for selecting one of the second plurality of rows;
- and
- a second redundant row;
- a built-in self test (BIST) portion having an output for providing an active BIST FAIL signal when a row associated with a row address in one of the first plurality of rows and second plurality of rows is defective;
- a control circuit coupled to the BIST portion and to the memory for replacing a defective row in the first plurality of rows with the second redundant row.
10 more elements
A semiconductor device comprising:
- a memory array having:
- a plurality of rows, each of the plurality of rows having a plurality of bit cells having output nodes coupled to a plurality of column nodes;
- a row decoder coupled to the plurality of rows for electrically coupling storage nodes associated with one of the plurality of rows to the plurality of column nodes;
- a sense amplifier coupled to the plurality of column nodes;
- a redundant row having a plurality of redundant bit cells, the plurality of redundant bit cells having output nodes coupled to one of the plurality of column nodes;
- a built-in self test (BIST) portion having an input node for receiving a row address and an output node for providing an active signal when a row associated with the row address in the plurality of rows is defective;
- a latch having a first input node coupled to the output node of the BIST portion, and a second input node coupled to the row address, an output node coupled to the row decoder and the redundant row for providing a latched address, the latch for latching an address of a defective row.
4 more elements
A method of decoding a memory having a plurality of rows, the method comprising:
- using built-in self test to identify a non-functional row of the plurality of rows;
- storing an address associated with the non-functional row;
- monitoring a current address to determine if a match exists between the non-functional address and the current address;
- when a match occurs, selecting a redundant row as an active row and disabling selection of the non-functional row;
- when a match does not occur, selecting the current row as the active row.
2 more elements
A method of decoding a memory having a plurality of rows, the method comprising:
- using built in self test to identify non-functional rows within the plurality of rows;
- for each non-functional row, setting a corresponding latch and storing an address of the non-functional row in volatile memory;
- providing the address corresponding to the non-functional row;
- preventing the non-functional row from being accessed based on the corresponding latch value;
- enabling a redundant row based on the address of the non-functional row.
2 more elements
Dependencies are inferred from the claim text.