Error correcting code retrofit method and apparatus for multiple memory configurations

An apparatus for encoding and decoding an incoming data word received from a computer system wherein said incoming data word is to be stored in one or more memory devices and wherein all of said one or more memory devices may have one of a plurality of memory configuration types, the apparatus comprising:

• a memory configuration indicator for indicating the memory configuration type for all of the one or more memory devices;
• a check bit generation circuit coupled to said memory configuration indicator and capable of coupling to said computer system for receiving said incoming data word, said check bit generation circuit encoding said incoming data word by generating a set of check bits, said check bits being generated by one of a plurality of operating modes for said check bit generation circuit, said check bits being based on the contents of the incoming data word and the operating mode of the check bit generation circuit, said operating mode being determined by the memory configuration type indication, said check bit generation circuit capable of coupling to said one or more memory devices and wherein said generated check bits are stored with said incoming data word in said one or more memory devices;
• an error detection circuit capable of coupling to the one or more memory device for receiving said stored encoded data word and said stored check bits, and coupled to said memory configuration type indicator, said error detection circuit decoding said encoded data word to determine if one or more bits included in the data word have been altered said data word being decoded by one of a plurality of decoding modes by said error detection circuit, said decoding being based upon the contents of the encoded data word, and the decoding mode of the error detection circuit, said decoding mode being determined by the memory configuration type indication;
• and
• an error correction circuit coupled to said error detection circuit and capable of coupling to said one or more memory devices and capable of coupling to said computer system, the error correction circuit receiving an indication from said error detection circuit and correcting the contents of said data word received from said one or more memory devices if said error detection circuit indicates that one or more bits of the data word have been altered, said error correction circuit capable of restoring one or more altered bits in the data word to their original values and passing said corrected data word to the computer system.