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AssigneeAxis Systems, Inc.
InventorsPing-Sheng Tseng, Sharon Sheau-Pyng Lin, Quincy Kun-Hsu Shen, Richard Yachyang Sun, Mike Mon Yen Tsai, Ren-Song Tsay, Steven Wang
Estimating the term…
The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. Each mode or combination of modes provides the following main features or combinations of main features: (1) switching among modes, manually or automatically; (2) compilation process to generate software models and hardware models; (3) component type analysis for generating hardware models; (4) software clock set-up to avoid race conditions through, in one embodiment, gated clock logic analysis and gated data logic analysis; (5) software clock implementation through, in one embodiment, clock edge detection in the software model to trigger an enable signal in the hardware model, send signal from the primary clock to the clock input of the clock edge register in the hardware model via the gated clock logic, send a clock enable signal to the enable input of the hardware model's register, send data from the primary clock register to the hardware model's register via the gated data logic, and reset the clock edge register disabling the clock enable signal to the enable input of the hardware model's registers; (6) log selective data for debug sessions and post-simulation analysis; and (7) combinational logic regeneration.
A method of simulating a circuit in a simulation system, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising steps:
A method of simulating a circuit, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising steps:
A method of simulating a circuit, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising steps:
A method of simulating a circuit in the environment of the circuit's target system, comprising steps:
A method of evaluating data in a circuit during a simulation process, comprising:
A method of controlling a simulation system, the simulation system having a software model and a hardware model of a circuit to be simulated, comprising steps:
A simulation system operating in a host computer system for simulating a behavior of a circuit, the host computer system including a central processing unit (CPU), main memory, and a local bus coupling the CPU to main memory and allowing communication between the CPU and main memory, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:
A verification system operating in a host computer system for verifying a behavior of a circuit, the host computer system including a central processing unit (CPU), memory, and a local bus coupling the CPU to memory and allowing communication between the CPU and memory, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:
A verification system operating in a host computer system for verifying a behavior of a circuit, the host computer system including a central processing unit (CPU), memory, and a system bus coupling the CPU to memory and allowing communication between the CPU and memory, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:
A design verification system operating in a host computer system for verifying a behavior of a circuit design, the host computer system including a central processing unit (CPU), memory, and a system bus coupling the CPU to memory and allowing communication between the CPU and memory, the circuit design represented by a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:
Dependencies are inferred from the claim text.