Short channel IGBT with improved forward voltage drop and improved switching power loss

A method of manufacture of a power semiconductor device comprising the steps of:

• introducing carriers of a first conductivity type into the exposed surface of a thin semiconductor chip which is of the first conductivity type and diffusing said carriers to a first depth into said substrate to form a region of increased conduction;
• forming a first mask layer having openings which overlie said region of increased conduction and applying a first given concentration of carriers of a second conductivity type, which is of opposite conductivity type to said first conductivity type, to said chip surface through said openings;
• forming a thin gate dielectric and a conductive gate electrode over at least portions of the surface of said region of increased conduction;
• forming a second mask layer having openings which surround and are at least adjacent to the locations of respective ones of said first mask layer openings and bounded by respective areas of said thin gate dielectric, and introducing a second given concentration of carriers of the second conductivity type, which is less than said first given concentration, to said chip through said second mask layer openings;
• diffusing said carriers of said first and second given concentrations of said second conductivity type at about a temperature of 1,175.degree. C. for a time ranging from 60 to 90 minutes, with said carriers of said first given concentration forming a body of relatively high concentration and said carriers of said second given concentration forming a relatively low concentration channel region which surrounds said body of relatively high concentration and underlies said thin gate dielectric, said diffusion permitting increased lifetime killing treatment;
• introducing a high concentration of carriers of said first conductivity type through said second mask openings and diffusing said carriers to form shallow source regions which diffuse laterally to underlie said thin gate dielectric and bound the inner edge of said low concentration channel region;
• and forming a source electrode on said source regions and a drain electrode which is electrically connected to said chip.