Arrangement for asynchronous decimation using a frequency ratio estimator and method thereof

A digital signal processing system for processing an input signal received at a first rate and converting the input signal to an output signal generated at a second rate, the system comprising:

• a first-in-first-out output buffer circuit having a set of data storage registers arranged to receive computed data samples for storage at a controlled rate and to pass the received computed data samples at a second rate;
• a current capacity signal generated by the output buffer circuit and indicative of current use of the data storage registers;
• a frequency ratio estimation circuit arranged to respond to the current capacity signal by providing an estimate of the actual ratio between the first rate and the second rate;
• a control circuit, responsive to the frequency ratio estimation circuit, for generating the controlled rate at which the computed data samples are to be passed to the output buffer circuit;
• and
• a digital processing circuit constructed and arranged to receive the data samples at a first rate and pass them to the output buffer circuit at the controlled rate and to output corresponding processed data samples at the second rate.

A method for converting an input signal received at a first rate to an output signal generated at a second lower rate, comprising:

• using a set of data storage registers as an output buffer for receiving computed data samples for storage at a controlled rate and for passing the data samples as outputs at a second rate;
• providing a quantity signal to indicate the quantity of the data samples that are currently stored in the set of data storage registers;
• estimating the actual ratio between the first rate and the second rate in response to the quantity signal;
• and
• in response to estimating the actual ratio, generating the controlled rate at which the data samples are to be passed to the set of data registers and outputting the data samples to the output at the second rate.

A communications system, comprising:

• a signal generator providing a input signal at an output port of the signal generator;
• a data sampling conversion arrangement including
• an output buffer having a set of data storage registers arranged to pass processed data samples at a variable rate, the data samples being produced from input samples received at a first rate according to a first clock signal,
• a current capacity signal generated by the output buffer circuit and indicative of current use of the set of data storage registers,
• a data clocking circuit arranged to generate a second clock signal,
• a ratio estimator arranged to provide an estimate of the actual ratio between the first rate and a second rate defined in synchronism with the second clock signal in response to the current capacity signal,
• a controller responsive to at least one of the first and second clock signals and to the ratio estimation circuit and arranged to control a variable rate at which the data storage registers receive the processed data samples;
• and
• a signal conditioner configured and arranged to respond to the data samples received at the first rate and to pass them to the data storage registers and to provide an output signal in response thereto having a second rate defined in synchronism with the second clock signal.