Memory device with pipelined column address path

A packetized memory device, comprising:

• a memory array including a plurality of banks;
• an address capture circuit adapted to capture a first address and a bank address from an address bus;
• a first address latch coupled to the address capture circuit and responsive to a latch signal to latch the captured first address;
• a bank address latch coupled to the address capture circuit and responsive to the latch signal to latch the captured bank address;
• data transfer circuitry coupled between the first address latch and the memory array and between the bank address latch and the memory array, the data transfer circuitry being responsive to the latched first and bank addresses to activate a column of the array corresponding to the latched first address in one of the banks corresponding to the latched bank address.

A packetized memory device, comprising:

• a memory array;
• command latches having input terminals adapted to receive command packets including a row address or a column address and including a bank address;
• a first address capture circuit coupled to the command latch and responsive to capture the row or column address from the command latch;
• a bank address capture circuit coupled to the command latch and responsive to capture the bank address from the command latch;
• a row or column address latch having an input terminal coupled to the address capture circuit and a control input, the row or column address latch being responsive to a control signal at the control terminal to latch the captured row or column address from the address capture circuit, the row or column address latch further including an output terminal;
• a bank address latch having an input terminal coupled to the bank address capture circuit and a bank control input, the bank address being responsive to the control signal to latch the bank address from the bank address latch;
• and
• a row or column decoder coupled between the memory array and the output terminal of the row or column latch, the row or column decoder being responsive to activate a row or column of the memory array responsive to the latched row or column address.

A computer system, comprising:

• a processor;
• an input device coupled to the processor;
• an output device coupled to the processor;
• a storage device coupled to the processor;
• a bus coupled to the processor;
• and
• a memory device including:
• a memory array including a plurality of banks;
• command latches coupled to the bus, and adapted to receive signals including a row or column address from the bus;
• a first address capture circuit coupled to the command latch and responsive to capture the row or column address from the command latch;
• a bank address capture circuit coupled to the command latch and responsive to capture the bank address from the command latch;
• a row or column address latch having an input terminal coupled to the address capture circuit and a control input, the row or column address latch being responsive to a control signal to latch the captured row or column address from the address capture circuit in response to a control signal at the control terminal, the row or column address latch further including an output terminal;
• a bank address latch having an input terminal coupled to the bank address capture circuit and a bank control input, the bank address being responsive to the control signal to latch the bank address from the bank address latch;
• and
• a row or column decoder coupled between the memory array and the output terminal of the row or column latch, the row or column decoder being responsive to activate a row or column of the memory array responsive to the latched row or column address.

A method of activating a row or column of a memory array in a packetized memory system, comprising:

• producing a clock signal;
• latching a first command packet responsive to the clock signal;
• latching a second command packet responsive to the clock signal;
• capturing a first set of addresses from the latched first command packet, the captured first set including a first bank address and a first address portion;
• latching the captured bank address responsive to a selected first transition of the clock signal;
• latching a captured first address portion responsive to the selected first transition;
• supplying the latched bank address portion and the latched first address portion to an I/O circuit responsive to a second selected transition of the clock signal;
• and
• activating a first row or column of the memory array responsive to the supplied latched bank address and first address portion.

A method of transferring data between a memory device and a data bus, comprising the steps of:

• receiving a first address and a first bank address at an externally accessible address input;
• latching the first address;
• latching the first bank address;
• decoding the latched first address;
• reading data from or writing data to a location indicated by the decoded first address in a bank corresponding to the first bank address;
• after latching the first and a first bank addresses and before completing the step of reading data into or writing data from the location indicated by the decoded first address, receiving a second address at the address input;
• and
• latching the second address.