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US 6,005,778 AGranted
Chip stacking and capacitor mounting arrangement including spacers
AssigneeHoneywell Inc.
InventorsRichard K. Spielberger, Ronald J. Jensen, Charles J. Speerschneider
Life of this patent
Estimating the term…
Abstract
Chip stacking and capacitor mounting arrangement including a planar spacer separating a first die and a second die. A conductive spacer provides for backside chip grounding in one application and provides for capacitor mounting in another application.
Claims23
Component stacking arrangement comprising:
- a die mounting surface;
- a first die secured to said die mounting surface;
- a first plurality of thin wires extending from a plurality of first bonding pads on said first die to a second plurality of bonding pads external to said first die;
- spacer means located within an area at least partially bounded by said first plurality of bonding pads, said spacer means secured at a first surface of said first die, said spacer means having an outer tier and a central tier with said tiers having electrically interconnected conductive surfaces;
- at least a first conductor electrically connecting said conductive surface of said outer tier to a first voltage;
- and
- a component having a conductive backside, said component secured at said conductive backside to said spacer means, with said spacer means having a thickness such that a surface of said component facing said first die is spaced further from said first die than a highest point of said first plurality of thin wires and a highest point of said first conductor.
4 more elements
Component stacking arrangement, comprising:
- a chip mounting surface;
- a first chip attached to said surface;
- a multiplicity of thin wires connecting bonding pads on said first chip to bonding pads external to said first chip;
- a spacer means having a first and second tier having electrically conducting and electrically connected first and second surfaces, said first tier to be of planar dimensions fitting within a space defined by said bonding pads on said first chip and said second tier smaller in planar dimension than said first tier;
- conductor means extending from said first tier to a first voltage;
- and
- a second chip secured to said second surface on said spacer means, with said spacer means being of such thickness as to allow clearance for the highest reach of said multiplicity of thin wires and said conductor means from the lowest most surface of said second chip.
4 more elements
Component stacking arrangement comprising:
- a die mounting surface;
- a first die secured to said die mounting surface;
- a first plurality of thin wires extending from a plurality of bonding pads on said first die;
- first spacer means having a conductive surface, said first spacer means located within an area partially bounded by said plurality of bonding pads and having an extended portion;
- first conductor means extending from said conductive surface of said extended portion to a first voltage;
- and
- a second component having a conductive backside, said second component secured to said conductive surface at said conductive backside with said extended portion extending beyond a perimeter of said second component in a first direction.
4 more elements
Dependencies are inferred from the claim text.