High-order multipath operational amplifier with dynamic offset reduction, controlled saturation current limiting, and current feedback for enhanced conditional stability

A conditionally-stable multipath operational amplifier comprising, in combination:

• at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output;
• and
• a relatively high-frequency bypass path from the signal input to a last one of the integrator stages in the low-frequency path;
• and
• an intermediate bypass path from the signal input to a second one of the integrator stages in the low-frequency path for bypassing a first one of the integrator stages in the relatively low-frequency path;
• wherein the first one of the integrator stages includes a differential amplifier and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the first one of the integrator stages;
• and
• further comprising an analog low-pass filter in the low-frequency path between the differential amplifier and the second one of the integrator stages to prevent artifacts of dynamic offset reduction from reaching the second one of the integrator stages.

A conditionally-stable operational amplifier comprising, in combination:

• at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output;
• and
• a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path;
• wherein the low-frequency path and the relatively high-frequency path converge at a current summing node combining current from a current source in the low-frequency path with current from a current source in the relatively high-frequency path, the current source in the relatively high-frequency path having a first saturation current limit, the current source in the low-frequency path having a second saturation current limit, and the first and second saturation current limits have values so that the relatively high-frequency path is not saturated when the low-frequency path saturates.

A conditionally-stable operational amplifier comprising, in combination:

• a voltage signal input;
• at least three integrator stages connected to provide a low-frequency path from the voltage signal input to a signal output;
• a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path;
• a current feedback input;
• and
• a shunt resistance from the current feedback input to a signal ground, wherein the conditionally-stable operational amplifier has an open-loop gain from said voltage signal input to said signal output inversely proportional to said shunt resistance.

A conditionally-stable operational amplifier comprising, in combination:

• at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output;
• a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path;
• and
• a current feedback input, wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented at the current feedback input;
• wherein the relatively high-frequency path includes a controlled voltage source applying a voltage to the current feedback input, the voltage being responsive to a signal on the signal input, and an output stage applying an output signal to the signal output in response to current flow through the resistance presented at the current feedback input.

A conditionally-stable operational amplifier comprising, in combination:

• at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output;
• a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path;
• wherein a first one of said integrator stages has a differential amplifier including inputs that are positive and negative in polarity with respect to the signal output at zero frequency, the differential amplifier producing a difference signal responsive to a difference in voltage between the positive and negative inputs of the differential amplifier;
• and
• further including a current feedback input in the high-frequency path connected to the differential amplifier to assert a voltage on the current feedback input responsive to the difference signal of the differential amplifier;
• and
• wherein a last one of the integrator stages in the low-frequency path is responsive to current flowing from said current feedback input.

An amplifier circuit comprising, in combination:

• a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output;
• and
• a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output;
• wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage;
• and
• wherein the conditionally-stable operational amplifier has an open-loop unit and frequency for unity gain from said signal input to said signal output, the conditionally-stable operational amplifier has at least 180 decrees of phase lap from said signal input to said signal output for a frequency less than the open-loop unity gain frequency, and the phase lag from said signal input to said signal output decreases to less than 180 degrees as frequency increases to the open-loop unity gain frequency.

An amplifier circuit comprising, in combination:

• a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output;
• and
• a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output;
• wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage;
• and
• wherein the resistor feedback network is adjustable to adjust the fraction of the signal from the signal output which is applied to the negative feedback input.

An amplifier circuit comprising, in combination:

• a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output;
• and
• a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output;
• wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having, a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage;
• and
• wherein the dynamic offset reduction circuit includes at least one chopper for chopper-stabilizing the differential amplifier.

An amplifier circuit comprising in combination:

• a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output;
• and
• a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output;
• wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and
• wherein the dynamic offset reduction circuit has a clock input for accepting at least one clock signal and produces undesirable artifacts from said clock signal, and further including an analog low-pass filter connected to the differential amplifier to prevent the undesirable artifacts from passing from the dynamic offset reduction circuit to the signal output.

An amplifier circuit comprising, in combination:

• a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output;
• and
• a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output;
• wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and
• further including a bypass path from the negative feedback input to the signal output for bypassing the differential amplifier, the bypass path merging at a summing node with a low-frequency path from the differential amplifier to the signal output, the summing node combining a signal from a first signal source in the bypass path with a signal from a second signal source in the low-frequency path, the first signal source having a first saturation limit, the second signal source having a second saturation limit, and the first and second saturation limits having values so that the bypass path is not saturated when the low-frequency path saturates.

An amplifier circuit comprising, in combination:

• a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output;
• and
• a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output;
• wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and
• wherein the negative feedback input is a current feedback input, and wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented by the resistor feedback network to the current feedback input.

An amplifier circuit comprising, in combination:

• a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output;
• and
• a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output;
• wherein the conditionally-stable operational amplifier includes at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output;
• and
• a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path;
• wherein the low-frequency path and the relatively high-frequency path converge at a summing node combining a signal from a first signal source in the low-frequency path with a signal from a second signal source in the relatively high-frequency path, the first signal source has a first saturation limit, the second signal source has a second saturation limit, and the first and second saturation limits have values so that the relatively high-frequency path is not saturated when the low-frequency path saturates.

A method of amplifying a signal, comprising the steps of:

• (a) passing a first portion of the signal through at least three integrator stages in a low-frequency path from a signal input to a signal output, a first one of the integrator stages in the low-frequency path including a differential amplifier that amplifies the signal before passing the signal to a next one of the integrator stages in the low-frequency path;
• and
• passing a second portion of the signal through a bypass path from the signal input to the signal output for bypassing the first one of the integrator stages in the low-frequency path;
• wherein the method further includes dynamically reducing offset of the first one of the integrator stages in response to at least one clock signal.

A method of amplifying a signal, comprising the steps of:

• (a) passing a first portion of the signal through at least three integrator stages in a low-frequency path from a signal input to a signal output;
• (b) passing a second portion of the signal through a bypass path around at least one of the integrator stages in the low-frequency path;
• and
• (c) combining the first portion of the signal passing from said at least one of the integrator stages with the second portion of the signal passing from the bypass path to produce a combined signal that is passed to the signal output;
• wherein the first portion of the signal passing from said at least one of the integrator stages is combined with the second portion of the signal passing from the bypass path by
• (i) converting the first portion of the signal from said at least one of the integrator stages to a first current limited to a first saturation current level,
• (ii) converting the second portion of the signal conveyed by the bypass path to a second current limited to a second saturation current level, the first and second saturation current levels having been preset so that saturation in the low-frequency path occurs before saturation in the bypass path, and
• (iii) summing the first current with the second current to produce a combined current.

A method of amplifying a signal using a conditionally-stable operational amplifier having at least three integrator stages in a low-frequency path from a signal input to a signal output and having a bypass path for effectively bypassing at least one of the integrators at a relatively high frequency, said method comprising the steps of:

• (a) applying the signal to the signal input;
• (b) converting the signal in the operational amplifier to a voltage applied to a current feedback input;
• (c) producing, in a resistance connected to the current feedback input, a current substantially proportional to the voltage applied to the current feedback input;
• and
• (d) producing, at the signal output, an output signal responsive to said current substantially proportional to the voltage applied to the current feedback input;
• wherein the method includes passing at least a portion of the signal through the bypass path around said at least one of the integrators at a relatively high frequency.

A signal processing system comprising, in combination,

• a conditionally-stable operational amplifier for amplifying an analog signal to produce an amplified analog signal;
• a feedback network connected to the conditionally-stable operational amplifier for setting a closed-loop gain for the conditionally-stable operational amplifier;
• and
• an analog-to-digital converter for converting the amplified analog signal to a corresponding digital signal;
• wherein the conditionally-stable operational amplifier includes at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output, a relatively high-frequency bypass path from the signal input to the signal output for bypassing a first one of the integrator stages in the low-frequency path, and, in the first one of the integrator stages, a differential amplifier and a dynamic offset reduction circuit responsive to a clock signal and connected to the differential amplifier to provide a reduction in differential offset voltage of the first one of the integrator stages.

A signal processing system for amplifying an analog differential signal including a first analog signal and a second analog signal, said system comprising, in combination:

• a first conditionally-stable operational amplifier for amplifying the first analog signal to produce a first amplified analog signal, the first conditionally-stable operational amplifier having a first signal input for receiving the first analog signal, a first negative feedback input, and a first signal output for providing the first amplified analog signal;
• a second conditionally-stable operational amplifier for amplifying the second analog signal to produce a second amplified analog signal, the second conditionally-stable operational amplifier having a second signal input for receiving the second analog signal, a second negative feedback input, and a second signal output for providing the second amplified analog signal;
• a resistor feedback network connected between said first signal output and said second output and having a first node connected to said first negative feedback input and a second node connected to said second negative feedback input so that said first conditionally-stable operational amplifier has a first closed-loop gain for amplifying said first analog signal and said second conditionally-stable operational amplifier has a second closed loop gain for amplifying said second analog signal, said first closed-loop gain being substantially equal to said second closed-loop gain;
• and
• an analog-to-digital converter for converting the first amplified analog signal and the second amplified analog signal to a corresponding digital signal representing a difference between the first amplified analog signal and the second amplified analog signal;
• wherein the first conditionally-stable operational amplifier includes a signal path from the first signal input to the first signal output including a first amplifier stage having a first differential amplifier for amplifying a difference between the first analog input signal from the first signal input and a first feedback signal from the first negative feedback input, and a first dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the first amplifier stage;
• and
• wherein the second conditionally-stable operational amplifier includes a signal path from the second signal input to the second signal output including a second amplifier stage having a second differential amplifier for amplifying a difference between the second analog input signal from the second signal input and a second feedback signal from the second negative feedback input, and a second dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the second amplifier stage.