Clock recovery circuit

A clock recovery circuit comprising:

• means for generating, in accordance with a reference frequency, a recovered clock signal having a selected phase;
• an up/down detector constructed to produce a first pulse when the selected phase of the recovered clock signal is ahead of a phase of a data signal, and to produce a second pulse when the selected phase of the recovered clock signal is behind the phase of the data signal;
• a divider constructed to divide the number of first pulses, the number of second pulses, and the frequency of the recovered clock signal by a predetermined number and output the results thereof;
• and
• control logic constructed to cause, in accordance with the output of the divider, the means for generating the recovered clock signal to change the selected phase of the recovered clock signal.

A clock recover circuit comprising:

• a voltage controlled oscillator constructed to produce, in accordance with a reference frequency, a plurality of clock signals, each of the plurality of clock signals having a different phase and the plurality of clock signals having a common frequency;
• a plurality of non-linear digital to analog converters;
• a phase interpolator constructed to generate a recovered clock signal having the common frequency and a selected phase, the selected phase being interpolated from at least two of the plurality of clock signals in accordance with outputs from the non-linear digital to analog converters;
• an up/down detector constructed to produce a first pulse when the selected phase of the recovered clock signal is ahead of a phase of a data signal, and to produce a second pulse when the selected phase of the recovered clock signal is behind the phase of the data signal;
• a divider constructed to divide the number of first pulses, the number of second pulses, and the frequency of the recovered clock signal by a predetermined number and to output the results thereof;
• and
• control logic constructed to control, in accordance with the output of the divider, the plurality of non-linear digital to analog converters.

A clock recovery circuit comprising:

• a voltage controlled oscillator constructed to produce, in accordance with a reference frequency, a first clock signal having a phase of 0.degree., a second clock signal having a phase of 90.degree., a third clock signal having a phase of 180.degree., and a fourth clock signal having a phase of 270.degree., wherein the first, second, third, and fourth clock signals having a common frequency;
• four non-linear digital to analog converters;
• a phase interpolator constructed to generate, in accordance with outputs from the non-linear digital to analog converters, a recovered clock signal having the common frequency and a selected phase, the selected phase being interpolated from one of the first and second clock signals, the second and third clock signals, the third and fourth clock signals, and the fourth and first clock signals;
• an up/down detector constructed to produce a first pulse when the selected phase of the recovered clock signal is ahead of a phase of a data signal, and to produce a second pulse when the selected phase of the recovered clock signal is behind the phase of the data signal;
• a divider constructed to divide the number of first pulses, the number of second pulses, and the frequency of the recovered clock signal by a predetermined number and output the results thereof;
• and
• control logic constructed to control, in accordance with the output of the divider, the plurality of non-linear digital to analog converters.