Stable output bias current circuitry and method for low-impedance CMOS output stage

A CMOS output circuit including a bias circuit, the bias circuit including a first resistor coupled between a first supply voltage conductor and a first conductor, a first first-conductivity-type MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the first conductor, and a drain coupled to a second conductor, a second first-conductivity-type MOSFET having a source coupled to the first conductor, a gate coupled to the second conductor, and a drain coupled to a drain and gate of a first second-conductivity-type current mirror control MOSFET having a source coupled to a second supply voltage conductor, and a first second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to the second conductor, wherein the first first-conductivity-type MOSFET is biased at the edge of its strong inversion condition, the improvement comprising:

• (a) an error amplifier including
• i. a first second-conductivity-type input MOSFET, a gate of the first second-conductivity-type input MOSFET being coupled to a first input terminal,
• ii. a second second-conductivity-type input MOSFET, a gate of the second second-conductivity-type input MOSFET being coupled to a second input terminal,
• iii. a second second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to sources of the first and second second-conductivity-type input MOSFETs,
• iv. a first resistive load coupled between the first supply voltage conductor and a drain of the first second-conductivity-type input MOSFET;
• v. a second resistive load coupled between the first supply voltage conductor and a drain of the second second-conductivity-type input MOSFET;
• and
• (b) a first-conductivity-type output MOSFET having a gate coupled to the drain of the second second-conductivity-type input MOSFET, a source coupled to the first supply voltage conductor, and a drain coupled to an output terminal,
• a voltage produced by the error amplifier on the gate of the first-conductivity-type output MOSFET producing a stable quiescent bias current in the first-conductivity-type output MOSFET which is a predetermined multiple of a bias current flowing through the first first-conductivity-type MOSFET to cause the first-conductivity-type output MOSFET to be biased at the edge of its strong inversion condition similarly to the first first-conductivity-type MOSFET.

A method of operating a CMOS output circuit including a differential error amplifier to provide a stable quiescent bias current in a first-conductivity-type output MOSFET, the method comprising the steps of:

• (a) causing a first current equal to a threshold voltage of a first-conductivity-type reference MOSFET divided by the resistance of a reference resistor to flow through a current mirror control transistor;
• (b) causing a second current proportional to the first current to flow through the reference MOSFET by means of a first current mirror output transistor having a control electrode coupled to the control electrode of the current mirror control transistor and a first electrode coupled to a drain of the reference MOSFET, and controlling the first current in response to feedback from the reference MOSFET;
• (c) controlling a bias current in an error amplifier in response to the voltage of the control electrode of the current mirror control transistor;
• and
• (d) scaling the bias current of the error amplifier and the resistances of first and second resistive load devices of the error amplifier to produce a drive voltage which applies a quiescent gate-to-source voltage that is substantially equal to and tracks with the gate-to-source voltage of the reference MOSFET to the first-conductivity-type output MOSFET.

A CMOS output circuit including a bias circuit, the bias circuit including a first resistor coupled between a first supply voltage conductor and a first conductor, a first-conductivity-type reference MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the first conductor, and a drain coupled to a second conductor, a first transistor having a first electrode coupled to the first conductor, a control electrode coupled to the second conductor, and a second electrode coupled to a first electrode and control electrode of a first current mirror control transistor having a second electrode coupled to a second supply voltage conductor, and a first current mirror output transistor having a control electrode coupled to the control electrode of the current mirror control transistor, a first electrode coupled to the second supply voltage conductor, and a second electrode coupled to the second conductor, wherein the reference MOSFET is biased at the edge of its strong inversion condition, the improvement comprising:

• (a) an error amplifier including
• i. a first input transistor, a control electrode of the first input transistor being coupled to a first input terminal,
• ii. a second input transistor, a control electrode of the second input transistor being coupled to a second input terminal,
• iii. a second current mirror output transistor having a control electrode coupled to the control electrode of the current mirror control transistor, a first electrode coupled to the second supply voltage conductor, and a second electrode coupled to first electrodes of the first and second input transistors,
• iv. a first resistive load coupled between the first supply voltage conductor and a second electrode of the first input transistor;
• v. a second resistive load coupled between the first supply voltage conductor and a second electrode of the second input transistor;
• and
• (b) a first-conductivity-type output MOSFET having a gate coupled to the second electrode of the second input transistor, a source coupled to the first supply voltage conductor, and a drain coupled to an output terminal,
• a voltage produced by the error amplifier on the gate of the output MOSFET producing a stable quiescent bias current in the output MOSFET which is a predetermined multiple of a bias current flowing through the reference MOSFET to cause the output MOSFET to be biased at the edge of its strong inversion condition similarly to the reference MOSFET.