Method and apparatus for high-speed interconnect testing

In a method of testing interconnectivity of circuit boards having components operable at a high speed system clock, said method employing IEEE 1149.1 standard test methods in which test data is shifted into and from said components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between said Shift.sub.-- In and Shift.sub.-- Out operations, said components including a first group of components capable of performing said Update and Capture operations at the rate of said Test Clock only and a second group of components capable of performing said Update and Capture operations at said system clock, the improvement comprising:

• performing said Shift.sub.-- In operation in all of said components concurrently at the rate of said Test Clock;
• performing said Update and Capture Operations in said first group of components at the rate of said Test Clock;
• and
• performing said Update and Capture Operations in said second group of components at the rate of said system Clock.

In a method of testing interconnectivity of circuit boards having at least one component operable at a high speed system clock, said method employing IEEE 1149.1 standard test methods in which test data is shifted into and from said components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between said Shift.sub.-- In and Shift.sub.-- Out operations, said components including a first group of components capable of performing said Update and Capture operations at the rate of said Test Clock only and a second group of components capable of performing said Update and Capture operations at said system clock, the improvement comprising:

• performing said Shift.sub.-- In and Shift.sub.-- Out operations in all of said components at the rate of said Test Clock;
• Issuing an Update instruction;
• Issuing a Capture instruction a predetermined number of Test Clock cycles following said Update instruction;
• performing said Update operation in said first group of components in response to said Update instruction at the rate of said Test Clock;
• performing said Capture operation in said first group of components in response to said Capture instruction at the rate of said Test Clock;
• performing in said second group of components in response to said Update instruction:
• synchronizing said system clock with said test clock and delivering a synchronization signal to all components in said second group of components;
• performing a FastUpdate operation in said second group of components in response to said synchronization signal at the rate of said system clock a selective number of system clock cycles following said synchronization signal;
• performing a FastCapture operation in said second group of components prior to performing said Capture operation in said first group of components, said FastCapture operation being a predetermined number of system clock cycles following said synchronization signal and at the rate of said system clock;
• performing an output flip operation concurrently with or following said FastCapture operation and prior to said Shift.sub.-- Out operation, said output flip operation including inverting data output in said FastUpdate operation and re-inverting said data;
• and
• performing said Shift.sub.-- Out operation in all of said components concurrently at the rate of said Test Clock.

An integrated circuit, comprising:

• a core operable at said system clock and having a plurality of connections;
• boundary scan cells connected to each said connections and arranged in a scan chain interconnecting said connections;
• a test access port having inputs for receiving a test clock signal, a Test Mode Select signal;
• Test Data Input for receiving test data thereat;
• and outputs for Serial Data, an Update instruction and a Capture instruction;
• a Test Controller responsive to said Update instruction for producing a FastUpdate instruction and a FastCapture instruction and delivering said FastUpdate and FastCapture instructions in predetermined timed sequence to said boundary scans cells for executing Update and Capture operations at the rate of said system clock.

A boundary scan cell for inputting and/or outputting data to the core of an integrated circuit having a test access port and a test controller and operable at a system clock, said test access port having a data Shift.sub.-- In state for shifting data into said circuit, a data Shift.sub.-- Out state for shifting data captured from said core from said circuit, an Update state for effecting an Update operation and a Capture state for effecting a Capture operation, said boundary scan cell comprising:

• means operable at a test clock rate for receiving data during said Shift.sub.-- In state and outputting data during said Shift.sub.-- Out state;
• and
• means operable at said system clock rate and responsive to a FastUpdate signal output by said test controller for performing an Update operation;
• and
• means operable at said system clock rate and responsive to a FastCapture signal output by said test controller for performing a Capture operation.