Method and apparatus for complete hiding of the refresh of a semiconductor memory

A memory device comprising:

• a plurality of memory cells configured in a plurality of banks, wherein the memory cells must be periodically refreshed to retain data values;
• a control circuit for accessing and refreshing the memory cells, wherein the control circuit controls the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any accessing of the memory cells, the control circuit comprising a static random access memory (SRAM) cache;
• a read buffer, wherein the banks are coupled to the read buffer in parallel, and wherein data read from any one of the banks is provided to the read buffer;
• and
• a cache write buffer coupled between the SRAM cache and the read buffer.

A memory device comprising:

• a plurality of memory cells configured in a plurality of banks, wherein the memory cells must be periodically refreshed to retain data values;
• a control circuit for accessing and refreshing the memory cells, wherein the control circuit controls the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any accessing of the memory cells, the control circuit comprising a static random access memory (SRAM) cache;
• a read buffer, wherein the banks are coupled to the read buffer in parallel, and wherein data read from any one of the banks is provided to the read buffer;
• and
• a write buffer, wherein the banks are coupled to the write buffer in parallel, and wherein data is written from the write buffer to any one of the banks.

A method of operating a multi-bank memory comprising a plurality of memory cells that each must be refreshed within a predetermined refresh period to retain a data value, the method comprising the steps of:

• receiving external access requests to the multi-bank memory;
• generating refresh requests within the multi-bank memory;
• immediately processing each of the external access requests;
• and
• processing a refresh request to a bank of the multi-bank memory only if the bank has no pending external access request, whereby all of the memory cells are always refreshed within the predetermined refresh period.

A method of operating a multi-bank memory comprising a plurality of memory cells that require periodic refreshing and an SRAM cache, the method comprising the steps of:

• comparing a current access address with a cached address stored in the SRAM cache to determine when a cache miss occurs;
• accessing one of the banks identified by the current access address or the cached address when a cache miss occurs and a cache entry associated with the cached address is consistent with data stored by the memory cells;
• accessing both of the banks identified by the current access address and the cached address when a cache miss occurs and a cache entry associated with the cached address is not consistent with data stored by the memory cells;
• generating refresh requests within the multi-bank memory;
• and
• performing a refresh operation for a bank of the multi-bank memory in response to a refresh request only if the bank is not being accessed because a cache miss has occurred.

A method of operating a multi-bank memory comprising plurality of memory banks having a plurality of memory cells that require periodic refreshing and an SRAM cache, the method comprising the steps of:

• comparing an external access address with a cached address stored in the SRAM cache to determine when a cache hit or a cache miss occurs;
• generating refresh requests within the multi-bank memory;
• determining if a refresh request is pending within a memory bank;
• and
• refreshing the memory bank in response to a pending refresh request only when a cache hit occurs or when the memory bank is not accessed as a result of a cache miss or when there is no external access.