Electrically erasable and programmable non-volatile memory device with testable redundancy circuits

A method for testing a nonvolatile storage element in a memory circuit, the storage element forming a component of a redundancy address register and used to store an address of a defective matrix memory cell to which a redundancy memory cell is mapped, the method comprising:

• coupling the storage element to a matrix bit line;
• coupling the bit line to an output terminal of the memory circuit;
• activating the storage element;
• and
• measuring at the output terminal a first current flowing through the storage element.

A method for testing a threshold voltage of a nonvolatile storage element in a memory circuit, the storage element used to store an address of a defective matrix memory cell to which a redundancy memory cell is mapped, the method comprising:

• charging a bit line to a first bit-line logic level, the bit line coupled to the storage element;
• comparing the logic level on the bit line with a test logic level to generate a first comparison logic level on an output terminal of the memory circuit;
• driving the storage element with a drive signal having an initial signal level that deactivates the storage element;
• gradually varying the drive signal to a voltage level that causes the storage element to drive a second bit-line logic level onto the bit line;
• toggling the first comparison logic level to a second comparison logic level in response to the second bit-line logic level;
• and
• equating a first threshold voltage of the storage element with the voltage level of the drive signal when the first comparison logic level toggles to the second comparison logic level.

A method for testing a threshold voltage of a nonvolatile storage element in a memory circuit, the storage element used to store an address of a defective matrix memory cell to which a redundancy memory cell is mapped, the method comprising:

• charging a bit line to a first bit-line logic level, the bit line coupled to the storage element;
• monitoring a current supplied by a power source to the bit line;
• driving the storage element with a drive signal having an initial voltage level that causes the storage element to draw an initial current from the power source;
• gradually varying the drive signal to a voltage level that causes the storage element to draw from the power source a current that is significantly different than the initial current;
• and
• equating a first threshold voltage with the voltage level of the drive signal when the power source first supplies the different current.

Electrically erasable and programmable non-volatile memory device, comprising at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and selecting respective redundancy columns when said defective columns are addressed, wherein said redundancy control circuit comprises second direct memory access test means activatable in a second test mode together with said first direct memory access test means for directly coupling memory elements of the defective-address storage means to respective second-level columns of the array, whereby said memory elements of the defective-address storage means can be directly coupled to output terminals of the memory device.