High speed, fine-resolution gain programmable amplifier

An integrated circuit comprising a differential amplifier for amplifying a differential input voltage, characterized in that said differential amplifier comprises:

• a first transconductance amplifier operative to convert said differential input voltage to a differential output current in accordance with a first transconductance thereof;
• a second transconductance amplifier biased so as to provide a second transconductance and operative to convert said differential output current to a differential output voltage, said second transconductance amplifier having substantially identical circuit topology as said first transconductance amplifier plus a pair of low impedance feedback paths connected between input/output terminals thereof of opposite polarity;
• and,
• a digital to analog converter (DAC) for converting a digital input code to an analog voltage, said analog voltage being applied to one of said first and second transconductance amplifiers to control the transconductance thereof;
• wherein the gain of said differential amplifier is a function of the ratio of said first transconductance to said second transconductance, and said first transconductance and said second transconductance vary by about the same percentage as a function of operating temperature such that said gain is substantially constant with operating temperature.

An integrated circuit comprising a differential amplifier for amplifying a differential input voltage, characterized in that said differential amplifier comprises:

• a first transconductance amplifier operative to convert said differential input voltage to a differential output current in accordance with a first transconductance thereof;
• a second transconductance amplifier biased so as to provide a second transconductance and operative to convert said differential output current to a differential output voltage, said second transconductance amplifier having a substantially identical circuit topology as said first transconductance amplifier plus a pair of low impedance feedback paths connected between input/output terminals thereof of opposite polarity;
• a digital to analog converter (DAC) for converting a digital input code to an analog voltage, said analog voltage being applied to one of said first and second transconductance amplifiers to control the transconductance thereof;
• wherein the gain of said differential amplifier is a function of the ratio of said first transconductance to said second transconductance, and said first transconductance and said second transconductance vary by about the same percentage as a function of operating temperature such that said gain is substantially constant with operating temperature;
• and,
• each of said first and second transconductance amplifiers comprises:
• first and second circuit parts, each circuit part having first and second n-channel field effect transistors (nFETS) and an operational amplifier, with source terminals of said first nFETs in the circuit parts being commonly connected to a point of low reference potential;
• each operational amplifier connected to receive an input transconductance control voltage at a non-inverting input terminal thereof, with an inverting terminal thereof being connected to a circuit node between a drain terminal of said first nFET and a source terminal of the second nFET in the associated circuit part, each second nFET having a drain terminal connected to a respective output resistance which is connected to a source of supply voltage;
• each operational amplifier having an output terminal coupled to a gate terminal of the second nFET in the associated circuit part, to thereby maintain the potential at said circuit node in the associated circuit part substantially equal to said input transconductance control voltage;
• and,
• said differential input voltage being applied across the gate terminals of said first nFETs of said first transconductance amplifier, said differential output current being applied to gate terminals of said first nFETs of said second transconductance amplifier, and said differential output voltage appearing across second and third circuit nodes corresponding to drain terminals of said second nFETs of said first and second circuit parts, respectively.