Flip chip circuit arrangement with redistribution layer that minimizes crosstalk

A circuit arrangement for a flip chip, comprising:

• (a) a logic circuit including a plurality of input/output (I/O) ports arranged generally along at least one peripheral edge thereof and disposed in at least one logic circuit layer;
• and
• (b) a redistribution circuit arrangement disposed in a redistribution layer, the redistribution circuit arrangement including a plurality of tiles arranged generally along the at least one peripheral edge of the logic circuit, each tile including:
• (1) a plurality of pads arranged in a linear array extending generally perpendicular to the peripheral edge of the logic circuit, the plurality of pads including first and second signal pads and a fixed potential pad;
• (2) a plurality of signal redistribution traces, the plurality of signal redistribution traces including first and second signal redistribution traces, the first signal redistribution trace electrically connecting one of the plurality of I/O ports to the first signal pad, and the second signal redistribution trace electrically connecting another of the plurality of I/O ports to the second signal pad;
• and
• (3) first and second shield traces, each electrically connected between a fixed potential and the fixed potential pad, the first shield trace interposed between the first and second signal redistribution traces, and the second shield trace interposed between one of the first and second signal redistribution traces and an adjacent tile in the redistribution layer such that each of the first and second signal redistribution traces in the plurality of tiles is bounded on both sides by a shield trace to reduce capacitive coupling with adjacent signal redistribution traces thereto.

A circuit arrangement for a flip chip, comprising:

• (a) a logic circuit including a plurality of input/output (I/O) ports arranged generally along at least one peripheral edge thereof and disposed in at least one logic circuit layer;
• and
• (b) a redistribution circuit arrangement disposed in a redistribution layer, the redistribution circuit arrangement including a plurality of tiles arranged generally along the at least one peripheral edge of the logic circuit, each tile including:
• (1) a plurality of pads arranged in a linear array extending generally perpendicular to the peripheral edge of the logic circuit, the plurality of pads including in order from the plurality of I/O ports a first fixed potential pad, first and second signal pads, a second fixed potential pad, and third and fourth fixed potential pads;
• (2) a plurality of signal redistribution traces, the plurality of signal redistribution traces including first, second, third and fourth signal redistribution traces respectively electrically connecting the first, second, third and fourth signal pads with selected I/O ports from the plurality of I/O ports, the first and third signal redistribution traces extending along a first side of the linear array and the second and fourth signal redistribution traces extending along a second side of the linear array;
• and
• (3) a plurality of shield traces, the plurality of shield traces including first, second, third and fourth shield traces, the first shield trace electrically connected between a first fixed potential and the first fixed potential pad and interposed between the first and second signal redistribution traces, and the second, third and fourth shield traces electrically connected between a second fixed potential and the second fixed potential pad, wherein the second shield trace is interposed between the first and third signal distribution traces, the third shield trace is interposed between the second and fourth signal distribution traces, and the fourth shield trace includes first and second portions extending on opposite sides of the linear array and electrically connected via an intermediate portion that extends between the third and fourth signal pads, the first portion extending along the first side of the linear array and interposed between the third signal redistribution trace and an adjacent tile in the plurality of tiles, such that each of the plurality of signal redistribution traces in the plurality of tiles is bounded on both sides by a shield trace to reduce capacitive coupling with adjacent signal redistribution traces thereto.

A circuit arrangement for a flip chip, comprising:

• (a) a logic circuit including a plurality of differential input/output (I/O) port pairs arranged generally along at least one peripheral edge thereof and disposed in at least one logic circuit layer, each differential I/O port pair configured to collectively transmit a differential signal;
• and
• (b) a redistribution circuit arrangement disposed in a redistribution layer, the redistribution circuit arrangement including a plurality of tiles arranged generally along the at least one peripheral edge of the logic circuit, each tile including:
• (1) a plurality of pads arranged in a linear array extending generally perpendicular to the peripheral edge of the logic circuit, the plurality of pads including in order from the plurality of differential I/O port pairs a first fixed potential pad, a first and second signal pads, a second fixed potential pad, and third and fourth fixed potential pads;
• (2) a plurality of signal redistribution traces, the plurality of signal redistribution traces including first, second, third and fourth signal redistribution traces, the first and second signal redistribution defining a first differential trace pair electrically connecting a first differential I/O port pair with the first and second signal pads and extending along a first side of the linear array, and the third and fourth signal redistribution traces defining a second differential trace pair electrically connecting a second differential I/O port pair with the third and fourth signal pads and extending along a second side of the linear array;
• and
• (3) a plurality of shield traces, the plurality of shield traces including first and second shield traces, the first shield trace electrically connected between a first fixed potential and the first fixed potential pad and interposed between the first and second differential trace pairs, and the second shield trace electrically connected between a second fixed potential and the second fixed potential pad and extending along the first side of the linear array immediately adjacent first differential trace pair such that the second shield trace is interposed between the first differential trace pair and an adjacent tile in the plurality of tiles, such that each of the differential trace pairs in the plurality of tiles are bounded on both sides by shield traces to reduce capacitive coupling with adjacent differential trace pairs thereto.