Elevated source/drain salicide CMOS technology
AssigneeAdvanced Micro Devices, Inc.
InventorsQi Xiang, Shekhar Pramanick
Life of this patent
Estimating the term…
Abstract
Low resistivity metal silicide layers are formed on a gate electrode and source/drain regions at an optimum thickness for reducing parasitic series resistances with an attendant consumption of silicon from the gate electrode and source/drain regions. Consumed silicon from the gate electrode and source/drain regions is then replaced employing metal induced crystallization, thereby avoiding a high leakage current. Embodiments include depositing a layer of amorphous silicon on the metal silicide layers and heating at a temperature of about 400.degree. C. to about 600.degree. C. initiating metal induced crystallization, thereby causing the metal silicide layers grow upwardly as silicon in the underlying gate electrode and source/drain regions is replaced.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- forming a structure comprising:
- a crystalline silicon substrate having a main surface;
- source/drain regions extending from the main surface into the substrate with a channel region therebetween;
- a gate dielectric layer on the substrate over the channel region;
- a polycrystalline silicon gate electrode, having side surfaces and a first height defined between a first upper surface and a lower surface, on the gate dielectric layer;
- and
- a dielectric sidewall spacer on each side surface of the gate electrode, leaving a portion of each source/drain region exposed;
- forming a metal silicide layer:
- on the first upper surface of the gate electrode, thereby reducing the first height of the gate electrode to a second height defined between a second upper surface and the lower surface;
- and on each exposed source/drain region extending below the main surface into each source/drain region;
- depositing a layer of amorphous silicon on the metal silicide layers and on the sidewall spacers;
- and
- heating to cause metal induced crystallization, thereby:
- crystallizing the amorphous silicon layers on the source/drain regions while the metal silicide layers on the source/drain regions move upwardly such that the metal silicide layers do not extend below the main surface;
- and
- crystallizing the amorphous silicon layer on the second upper surface gate electrode while the metal silicide layer on the gate electrode moves upwardly such that it does not extend below the first upper surface of the gate electrode.
A method of manufacturing a semiconductor device, the method comprising:
- forming a structure comprising:
- a crystalline silicon substrate having a main surface;
- source/drain regions extending from the main surface into the substrate with a channel region therebetween;
- a gate dielectric layer on the substrate over the channel region;
- a polycrystalline silicon gate electrode, having side surfaces and a first height defined between a first upper surface and a lower surface, on the gate dielectric layer;
- and
- a dielectric sidewall spacer on each side surface of the gate electrode leaving a portion of each source/drain region exposed;
- forming a metal silicide layer, comprising titanium silicide, nickel silicide or cobalt silicide:
- on and extending below the first upper surface of the gate electrode thereby reducing the first height of the gate electrode to a second height defined between a second upper surface and the lower surface;
- and on each exposed source/drain region extending below the main surface into each source/drain region, wherein silicon in the gate electrode and in each source/drain region is consumed during metal silicide formation;
- and
- replacing the consumed silicon in the gate electrode and source/drain regions while moving the metal silicide layers upwardly.
Dependencies are inferred from the claim text.