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AssigneeTelefonaktiebolaget LM Ericsson
InventorNianxiong Tan
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To convert an analog current to a digital signal using a high-speed pipelined analog-to-digigal (A/D) converter, the A/D converter may comprise a current sample- and hold (S/H) circuit at the input and several identical pipelined stages, where each stage contains a current S/H circuit, a current interstage low-resolution A/D converter and current references. To improve the speed of pipelined current-mode A/D converters the capacitive load seen by the output of every stage will be reduced. By adjusting the reference currents the power consumption will also be reduced. It is possible to achieve about 100 Msamples/s conversion rate and to reduce the power consumption by several times compared with existing designs. To increase the operation speed and to provide means to reduce the power consumption the pipelined current-mode A/D converter may comprise an S/H circuit (7) as the input and N pipelined stages (8), each of which contains an internal low-resolution A/D converter (9), a D/A converter (10), an S/H circuit (11), a reference current source (12) and an adder/subtractor (13). The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D converter and the interstage S/H circuit are timeinterleaved; and 2) the reference current to the D/A converter in every stage can be different.
A device to convert an analog current to a digital signal particularly where the device relates to the design of high-speed pipelined analog-to-digital (A/D) converters, characterized by comprising an S/H circuit (7) at an input and N pipelined stages (8), each of them comprising an internal low resolution A/D converter (9), a D/A converter (10), an S/H circuit (11), a reference current source (12) and an adder/subtractor (13), wherein every stage (8) does not have to be identical to any other, and wherein, in the stages (8), the inter stage A/D converter (9) and the S/H circuit (11) are timeinterleaved to reduce capacitive load in order to have high speed.
A method of performing pipelined analog-to-digital conversion, wherein bits of a digital output value are generated via a succession of hardware stages, each hardware stage utilizing a reference current to generate at least one bit of the digital output value, comprising the steps of:
A method of performing pipelined analog-to-digital conversion, wherein bits of a digital output value are generated via a succession of hardware stages, each hardware stage utilizing a reference current to generate at least one bit of the digital output value, comprising the steps of:
A pipelined analog-to-digital converter for converting an analog current to a digital signal comprising:
A pipelined analog-to-digital converter for converting an analog current to a digital signal comprising:
Dependencies are inferred from the claim text.