Circuit for comparing two electrical quantities provided by a first neuron MOS field effect transistor and a reference source

A binary multiplier cell for operation of a multiplier bit, a multiplicand bit, a sum bit of a preceding partial product and a carry bit of a preceding partial product as input potentials to form an output sum bit and an output carry bit, comprising:

• a first evaluator circuit for forming the output carry bit;
• a second evaluator circuit for forming the output sum bit;
• each of the first and second evaluator circuits having a first neuron MOS field effect transistor and a reference transistor, having a current mirror, an output of the first neuron MOS field effect transistor coupled via a first terminal to an output of the current mirror, and an output of the reference transistor coupled to an input of the current mirror, the first term final connected to at least one terminal of a first inverter unit at whose output a result signal pends, the result signal being a carry bit;
• a second inverter unit, whereby the output of the first inverter is connected at an input of the second inverter unit and a negated output carry bit is therefore present at an output of the second inverter unit;
• the multiplier bit, the multiplicand bit, the sum bit of a preceding partial product and the carry bit of a preceding partial product are applied weighted to gate terminals of the first neuron MOS field effect transistor of the first evaluator circuit and to gate terminals of the first neuron MOS field effect transistor of the second evaluator circuit;
• and
• the negated output carry bit is forwarded weighted to a further gate terminal of the first neuron MOS field effect transistor of the second evaluator circuit the output of said second inverter unit being connected to said further gate terminal.