High resistivity integrated circuit resistor

An integrated circuit resistor in a semiconductor substrate, which comprises:

• a contiguous first conductivity type region in the semiconductor substrate, wherein the first conductivity type region has a dopant depth that is approximately equal to a dopant depth of transistor source/drain regions of the first conductivity type elsewhere in the semiconductor substrate;
• at least two electrical contacts to the first conductivity type region for allowing current flow between the contacts through the first conductivity type region of the integrated circuit resistor;
• and
• at least one second conductivity type region in the semiconductor substrate such that the second conductivity type region at least partially intersects the first conductivity type region for increasing the resistance to the current flow between the contacts through the first conductivity type region of the integrated circuit resistor, wherein the second conductivity type region has a dopant depth that is approximately equal to a dopant depth of transistor source/drain regions of the second conductivity type elsewhere in the semiconductor substrate.

A complementary metal-oxide-semiconductor (CMOS) integrated circuit resistor in a semiconductor substrate, which comprises:

• a contiguous first conductivity type region in the semiconductor substrate, wherein the first conductivity type region has a dopant depth that is approximately equal to a dopant depth of transistor source/drain regions of the first conductivity type elsewhere in the semiconductor substrate;
• at least two electrical contacts to the first conductivity type region such that the first conductivity type region and the contacts determine a path of current flow between the electrical contacts through the first conductivity type region;
• and
• at least one second conductivity type region in the semiconductor substrate such that the second conductivity type region partially intersects the first conductivity type region, in the path of current flow between the electrical contacts, for increasing a resistance of the CMOS integrated circuit resistor, wherein the second conductivity type region has a dopant depth that is approximately equal to a dopant depth of transistor source/drain regions of the second conductivity type elsewhere in the semiconductor substrate.

A complementary metal-oxide-semiconductor (CMOS) integrated circuit resistor fabricated in a semiconductor substrate, the resistor comprising:

• a contiguous first conductivity type region in the semiconductor substrate, wherein the first conductivity type region has a dopant depth that is approximately equal to a dopant depth of transistor source/drain regions of the first conductivity type elsewhere in the semiconductor substrate;
• at least two electrical contacts to the first conductivity type region for allowing current flow between the contacts through the first conductivity type region of the integrated circuit resistor;
• and
• means for at least partially intersecting the first conductivity type region and increasing a resistance of the resistor, said means including at least one second conductivity type region in the semiconductor substrate such that the second conductivity type region partially intersects the first conductivity type region, in the path of current flow between the electrical contacts, for increasing a resistance of the CMOS integrated circuit resistor, wherein the second conductivity type region has a dopant depth that is approximately equal to a dopant depth of transistor source/drain regions of the second conductivity type elsewhere in the semiconductor substrate.

A integrated circuit resistor fabricated in a substrate having a surface, the resistor comprising:

• a contiguous first conductivity type region formed in the substrate, wherein the first conductivity type region has a dopant depth that is approximately equal to a dopant depth of a first conductivity type transistor source/drain region formed elsewhere in the substrate;
• at least two electrical contacts to the first conductivity type region for allowing current flow between the contacts through the first conductivity type region;
• and
• at least one second conductivity type region formed in the substrate such that the second conductivity type region at least partially intersects the first conductivity type region for increasing resistance to the current flow between the contacts, wherein the second conductivity type region has a dopant depth that is approximately equal to a dopant depth of a second conductivity type transistor source/drain region formed elsewhere in the substrate.

An integrated circuit resistor, in a semiconductor substrate, the resistor comprising:

• a p+ region in the substrate, wherein the p+ region has a dopant depth that is approximately equal to a dopant depth of p+ transistor source/drain regions elsewhere in the substrate;
• at least two electrical contacts to the p+ region, the contacts separated by a contiguous portion of the p+ region, the contiguous portion of the p+ region defining a path of current flow between the contacts;
• and
• at least one n+ region in the substrate and at least partially intersecting and obstructing the contiguous portion of the p+ region defining the path of current flow between the contacts, the n+ region providing an increased resistance structure in the path of current flow in the p+ region between the contacts, wherein the n+ region has a dopant depth that is approximately equal to a dopant depth of n+ transistor source/drain regions elsewhere in the substrate.

An integrated circuit resistor, in a semiconductor substrate, the resistor comprising:

• an n+ region in the substrate, wherein the n+ region has a dopant depth that is approximately equal to a dopant depth of n+ transistor source/drain regions elsewhere in the substrate;
• at least two electrical contacts to the n+ region, the contacts separated by a contiguous portion of the n+ region, the contiguous portion of the n+ region defining a path of current flow between the contacts;
• and
• at least one p+ region in the substrate and at least partially intersecting and obstructing the contiguous portion of the n+ region defining the path of current flow between the contacts, the p+ region providing an increased resistance structure in the path of current flow in the n+ region between the contacts, wherein the p+ region has a dopant depth that is approximately equal to a dopant depth of p+ transistor source/drain regions elsewhere in the substrate.